1/*
2 * Copyright (c) 2016 Cadence Design Systems, Inc.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6/**
7 * @file
8 * @brief Linker command/script file
9 *
10 * Linker script for the Xtensa platform.
11 */
12
13#include <zephyr/linker/sections.h>
14
15#include <zephyr/devicetree.h>
16#include <zephyr/linker/linker-defs.h>
17#include <zephyr/linker/linker-tool.h>
18
19#define RAMABLE_REGION RAM :sram0_phdr
20#define ROMABLE_REGION srom1_seg :srom1_phdr
21
22MEMORY
23{
24  dram1_0_seg :                       	org = 0x3FFC0000, len = 0x20000
25  dram0_0_seg :                       	org = 0x3FFE0000, len = 0x20000
26  iram0_0_seg :                       	org = 0x40000000, len = 0x178
27  iram0_1_seg :                       	org = 0x40000178, len = 0x8
28  iram0_2_seg :                       	org = 0x40000180, len = 0x38
29  iram0_3_seg :                       	org = 0x400001B8, len = 0x8
30  iram0_4_seg :                       	org = 0x400001C0, len = 0x38
31  iram0_5_seg :                       	org = 0x400001F8, len = 0x8
32  iram0_6_seg :                       	org = 0x40000200, len = 0x38
33  iram0_7_seg :                       	org = 0x40000238, len = 0x8
34  iram0_8_seg :                       	org = 0x40000240, len = 0x38
35  iram0_9_seg :                       	org = 0x40000278, len = 0x8
36  iram0_10_seg :                      	org = 0x40000280, len = 0x38
37  iram0_11_seg :                      	org = 0x400002B8, len = 0x8
38  iram0_12_seg :                      	org = 0x400002C0, len = 0x38
39  iram0_13_seg :                      	org = 0x400002F8, len = 0x8
40  iram0_14_seg :                      	org = 0x40000300, len = 0x38
41  iram0_15_seg :                      	org = 0x40000338, len = 0x8
42  iram0_16_seg :                      	org = 0x40000340, len = 0x38
43  iram0_17_seg :                      	org = 0x40000378, len = 0x48
44  iram0_18_seg :                      	org = 0x400003C0, len = 0x40
45  iram0_19_seg :                      	org = 0x40000400, len = 0x1FC00
46  srom0_seg :                         	org = 0x50000000, len = 0x300
47  srom1_seg :                         	org = 0x50000300, len = 0xFFFD00
48  RAM :                         	org = 0x60000000, len = 0x4000000
49#ifdef CONFIG_GEN_ISR_TABLES
50  IDT_LIST : org = 0x3ffbe000, len = 0x2000
51#endif
52}
53
54PHDRS
55{
56  dram1_0_phdr PT_LOAD;
57  dram1_0_bss_phdr PT_LOAD;
58  dram0_0_phdr PT_LOAD;
59  dram0_0_bss_phdr PT_LOAD;
60  iram0_0_phdr PT_LOAD;
61  iram0_1_phdr PT_LOAD;
62  iram0_2_phdr PT_LOAD;
63  iram0_3_phdr PT_LOAD;
64  iram0_4_phdr PT_LOAD;
65  iram0_5_phdr PT_LOAD;
66  iram0_6_phdr PT_LOAD;
67  iram0_7_phdr PT_LOAD;
68  iram0_8_phdr PT_LOAD;
69  iram0_9_phdr PT_LOAD;
70  iram0_10_phdr PT_LOAD;
71  iram0_11_phdr PT_LOAD;
72  iram0_12_phdr PT_LOAD;
73  iram0_13_phdr PT_LOAD;
74  iram0_14_phdr PT_LOAD;
75  iram0_15_phdr PT_LOAD;
76  iram0_16_phdr PT_LOAD;
77  iram0_17_phdr PT_LOAD;
78  iram0_18_phdr PT_LOAD;
79  iram0_19_phdr PT_LOAD;
80  srom0_phdr PT_LOAD;
81  srom1_phdr PT_LOAD;
82  sram0_phdr PT_LOAD;
83  sram0_bss_phdr PT_LOAD;
84}
85
86
87/*  Default entry point:  */
88ENTRY(CONFIG_KERNEL_ENTRY)
89
90/*  Memory boundary addresses:  */
91_memmap_mem_dram1_start = 0x3ffc0000;
92_memmap_mem_dram1_end   = 0x3ffe0000;
93_memmap_mem_dram0_start = 0x3ffe0000;
94_memmap_mem_dram0_end   = 0x40000000;
95_memmap_mem_iram0_start = 0x40000000;
96_memmap_mem_iram0_end   = 0x40020000;
97_memmap_mem_srom_start = 0x50000000;
98_memmap_mem_srom_end   = 0x51000000;
99_memmap_mem_sram_start = 0x60000000;
100_memmap_mem_sram_end   = 0x64000000;
101
102/*  Memory segment boundary addresses:  */
103_memmap_seg_dram1_0_start = 0x3ffc0000;
104_memmap_seg_dram1_0_max   = 0x3ffe0000;
105_memmap_seg_dram0_0_start = 0x3ffe0000;
106_memmap_seg_dram0_0_max   = 0x40000000;
107_memmap_seg_iram0_0_start = 0x40000000;
108_memmap_seg_iram0_0_max   = 0x40000178;
109_memmap_seg_iram0_1_start = 0x40000178;
110_memmap_seg_iram0_1_max   = 0x40000180;
111_memmap_seg_iram0_2_start = 0x40000180;
112_memmap_seg_iram0_2_max   = 0x400001b8;
113_memmap_seg_iram0_3_start = 0x400001b8;
114_memmap_seg_iram0_3_max   = 0x400001c0;
115_memmap_seg_iram0_4_start = 0x400001c0;
116_memmap_seg_iram0_4_max   = 0x400001f8;
117_memmap_seg_iram0_5_start = 0x400001f8;
118_memmap_seg_iram0_5_max   = 0x40000200;
119_memmap_seg_iram0_6_start = 0x40000200;
120_memmap_seg_iram0_6_max   = 0x40000238;
121_memmap_seg_iram0_7_start = 0x40000238;
122_memmap_seg_iram0_7_max   = 0x40000240;
123_memmap_seg_iram0_8_start = 0x40000240;
124_memmap_seg_iram0_8_max   = 0x40000278;
125_memmap_seg_iram0_9_start = 0x40000278;
126_memmap_seg_iram0_9_max   = 0x40000280;
127_memmap_seg_iram0_10_start = 0x40000280;
128_memmap_seg_iram0_10_max   = 0x400002b8;
129_memmap_seg_iram0_11_start = 0x400002b8;
130_memmap_seg_iram0_11_max   = 0x400002c0;
131_memmap_seg_iram0_12_start = 0x400002c0;
132_memmap_seg_iram0_12_max   = 0x400002f8;
133_memmap_seg_iram0_13_start = 0x400002f8;
134_memmap_seg_iram0_13_max   = 0x40000300;
135_memmap_seg_iram0_14_start = 0x40000300;
136_memmap_seg_iram0_14_max   = 0x40000338;
137_memmap_seg_iram0_15_start = 0x40000338;
138_memmap_seg_iram0_15_max   = 0x40000340;
139_memmap_seg_iram0_16_start = 0x40000340;
140_memmap_seg_iram0_16_max   = 0x40000378;
141_memmap_seg_iram0_17_start = 0x40000378;
142_memmap_seg_iram0_17_max   = 0x400003c0;
143_memmap_seg_iram0_18_start = 0x400003c0;
144_memmap_seg_iram0_18_max   = 0x40000400;
145_memmap_seg_iram0_19_start = 0x40000400;
146_memmap_seg_iram0_19_max   = 0x40020000;
147_memmap_seg_srom0_start = 0x50000000;
148_memmap_seg_srom0_max   = 0x50000300;
149_memmap_seg_srom1_start = 0x50000300;
150_memmap_seg_srom1_max   = 0x51000000;
151_memmap_seg_sram0_start = 0x60000000;
152_memmap_seg_sram0_max   = 0x64000000;
153
154_rom_store_table = 0;
155PROVIDE(_memmap_vecbase_reset = 0x40000000);
156PROVIDE(_memmap_reset_vector = 0x50000000);
157/* Various memory-map dependent cache attribute settings: */
158_memmap_cacheattr_wb_base = 0x00001110;
159_memmap_cacheattr_wt_base = 0x00001110;
160_memmap_cacheattr_bp_base = 0x00002220;
161_memmap_cacheattr_unused_mask = 0xFFFF000F;
162_memmap_cacheattr_wb_trapnull = 0x2222111F;
163_memmap_cacheattr_wba_trapnull = 0x2222111F;
164_memmap_cacheattr_wbna_trapnull = 0x2222111F;
165_memmap_cacheattr_wt_trapnull = 0x2222111F;
166_memmap_cacheattr_bp_trapnull = 0x2222222F;
167_memmap_cacheattr_wb_strict = 0xFFFF111F;
168_memmap_cacheattr_wt_strict = 0xFFFF111F;
169_memmap_cacheattr_bp_strict = 0xFFFF222F;
170_memmap_cacheattr_wb_allvalid = 0x22221112;
171_memmap_cacheattr_wt_allvalid = 0x22221112;
172_memmap_cacheattr_bp_allvalid = 0x22222222;
173PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
174
175SECTIONS
176{
177
178#include <zephyr/linker/rel-sections.ld>
179#include <zephyr/linker/llext-sections.ld>
180
181#ifdef CONFIG_GEN_ISR_TABLES
182#include <zephyr/linker/intlist.ld>
183#endif
184
185  .dram1.rodata : ALIGN(4)
186  {
187    _dram1_rodata_start = ABSOLUTE(.);
188    *(.dram1.rodata)
189    _dram1_rodata_end = ABSOLUTE(.);
190  } >dram1_0_seg :dram1_0_phdr
191
192  .dram1.literal : ALIGN(4)
193  {
194    _dram1_literal_start = ABSOLUTE(.);
195    *(.dram1.literal)
196    _dram1_literal_end = ABSOLUTE(.);
197  } >dram1_0_seg :dram1_0_phdr
198
199  .dram1.data : ALIGN(4)
200  {
201    _dram1_data_start = ABSOLUTE(.);
202    *(.dram1.data)
203    _dram1_data_end = ABSOLUTE(.);
204  } >dram1_0_seg :dram1_0_phdr
205
206  .dram1.bss (NOLOAD) : ALIGN(8)
207  {
208    . = ALIGN (8);
209    _dram1_bss_start = ABSOLUTE(.);
210    *(.dram1.bss)
211    . = ALIGN (8);
212    _dram1_bss_end = ABSOLUTE(.);
213    _memmap_seg_dram1_0_end = ALIGN(0x8);
214  } >dram1_0_seg :dram1_0_bss_phdr
215
216  .dram0.rodata : ALIGN(4)
217  {
218    _dram0_rodata_start = ABSOLUTE(.);
219    *(.dram0.rodata)
220    _dram0_rodata_end = ABSOLUTE(.);
221  } >dram0_0_seg :dram0_0_phdr
222
223  .dram0.literal : ALIGN(4)
224  {
225    _dram0_literal_start = ABSOLUTE(.);
226    *(.dram0.literal)
227    _dram0_literal_end = ABSOLUTE(.);
228  } >dram0_0_seg :dram0_0_phdr
229
230  .dram0.data : ALIGN(4)
231  {
232    _dram0_data_start = ABSOLUTE(.);
233    *(.dram0.data)
234    _dram0_data_end = ABSOLUTE(.);
235  } >dram0_0_seg :dram0_0_phdr
236
237  .dram0.bss (NOLOAD) : ALIGN(8)
238  {
239    . = ALIGN (8);
240    _dram0_bss_start = ABSOLUTE(.);
241    *(.dram0.bss)
242    . = ALIGN (8);
243    _dram0_bss_end = ABSOLUTE(.);
244    _memmap_seg_dram0_0_end = ALIGN(0x8);
245  } >dram0_0_seg :dram0_0_bss_phdr
246
247  .WindowVectors.text : ALIGN(4)
248  {
249    _WindowVectors_text_start = ABSOLUTE(.);
250    KEEP (*(.WindowVectors.text))
251    _WindowVectors_text_end = ABSOLUTE(.);
252    _memmap_seg_iram0_0_end = ALIGN(0x8);
253  } >iram0_0_seg :iram0_0_phdr
254
255  .Level2InterruptVector.literal : ALIGN(4)
256  {
257    _Level2InterruptVector_literal_start = ABSOLUTE(.);
258    *(.Level2InterruptVector.literal)
259    _Level2InterruptVector_literal_end = ABSOLUTE(.);
260    _memmap_seg_iram0_1_end = ALIGN(0x8);
261  } >iram0_1_seg :iram0_1_phdr
262
263  .Level2InterruptVector.text : ALIGN(4)
264  {
265    _Level2InterruptVector_text_start = ABSOLUTE(.);
266    KEEP (*(.Level2InterruptVector.text))
267    _Level2InterruptVector_text_end = ABSOLUTE(.);
268    _memmap_seg_iram0_2_end = ALIGN(0x8);
269  } >iram0_2_seg :iram0_2_phdr
270
271  .Level3InterruptVector.literal : ALIGN(4)
272  {
273    _Level3InterruptVector_literal_start = ABSOLUTE(.);
274    *(.Level3InterruptVector.literal)
275    _Level3InterruptVector_literal_end = ABSOLUTE(.);
276    _memmap_seg_iram0_3_end = ALIGN(0x8);
277  } >iram0_3_seg :iram0_3_phdr
278
279  .Level3InterruptVector.text : ALIGN(4)
280  {
281    _Level3InterruptVector_text_start = ABSOLUTE(.);
282    KEEP (*(.Level3InterruptVector.text))
283    _Level3InterruptVector_text_end = ABSOLUTE(.);
284    _memmap_seg_iram0_4_end = ALIGN(0x8);
285  } >iram0_4_seg :iram0_4_phdr
286
287  .Level4InterruptVector.literal : ALIGN(4)
288  {
289    _Level4InterruptVector_literal_start = ABSOLUTE(.);
290    *(.Level4InterruptVector.literal)
291    _Level4InterruptVector_literal_end = ABSOLUTE(.);
292    _memmap_seg_iram0_5_end = ALIGN(0x8);
293  } >iram0_5_seg :iram0_5_phdr
294
295  .Level4InterruptVector.text : ALIGN(4)
296  {
297    _Level4InterruptVector_text_start = ABSOLUTE(.);
298    KEEP (*(.Level4InterruptVector.text))
299    _Level4InterruptVector_text_end = ABSOLUTE(.);
300    _memmap_seg_iram0_6_end = ALIGN(0x8);
301  } >iram0_6_seg :iram0_6_phdr
302
303  .Level5InterruptVector.literal : ALIGN(4)
304  {
305    _Level5InterruptVector_literal_start = ABSOLUTE(.);
306    *(.Level5InterruptVector.literal)
307    _Level5InterruptVector_literal_end = ABSOLUTE(.);
308    _memmap_seg_iram0_7_end = ALIGN(0x8);
309  } >iram0_7_seg :iram0_7_phdr
310
311  .Level5InterruptVector.text : ALIGN(4)
312  {
313    _Level5InterruptVector_text_start = ABSOLUTE(.);
314    KEEP (*(.Level5InterruptVector.text))
315    _Level5InterruptVector_text_end = ABSOLUTE(.);
316    _memmap_seg_iram0_8_end = ALIGN(0x8);
317  } >iram0_8_seg :iram0_8_phdr
318
319  .DebugExceptionVector.literal : ALIGN(4)
320  {
321    _DebugExceptionVector_literal_start = ABSOLUTE(.);
322    *(.DebugExceptionVector.literal)
323    _DebugExceptionVector_literal_end = ABSOLUTE(.);
324    _memmap_seg_iram0_9_end = ALIGN(0x8);
325  } >iram0_9_seg :iram0_9_phdr
326
327  .DebugExceptionVector.text : ALIGN(4)
328  {
329    _DebugExceptionVector_text_start = ABSOLUTE(.);
330    KEEP (*(.DebugExceptionVector.text))
331    _DebugExceptionVector_text_end = ABSOLUTE(.);
332    _memmap_seg_iram0_10_end = ALIGN(0x8);
333  } >iram0_10_seg :iram0_10_phdr
334
335  .NMIExceptionVector.literal : ALIGN(4)
336  {
337    _NMIExceptionVector_literal_start = ABSOLUTE(.);
338    *(.NMIExceptionVector.literal)
339    _NMIExceptionVector_literal_end = ABSOLUTE(.);
340    _memmap_seg_iram0_11_end = ALIGN(0x8);
341  } >iram0_11_seg :iram0_11_phdr
342
343  .NMIExceptionVector.text : ALIGN(4)
344  {
345    _NMIExceptionVector_text_start = ABSOLUTE(.);
346    KEEP (*(.NMIExceptionVector.text))
347    _NMIExceptionVector_text_end = ABSOLUTE(.);
348    _memmap_seg_iram0_12_end = ALIGN(0x8);
349  } >iram0_12_seg :iram0_12_phdr
350
351  .KernelExceptionVector.literal : ALIGN(4)
352  {
353    _KernelExceptionVector_literal_start = ABSOLUTE(.);
354    *(.KernelExceptionVector.literal)
355    _KernelExceptionVector_literal_end = ABSOLUTE(.);
356    _memmap_seg_iram0_13_end = ALIGN(0x8);
357  } >iram0_13_seg :iram0_13_phdr
358
359  .KernelExceptionVector.text : ALIGN(4)
360  {
361    _KernelExceptionVector_text_start = ABSOLUTE(.);
362    KEEP (*(.KernelExceptionVector.text))
363    _KernelExceptionVector_text_end = ABSOLUTE(.);
364    _memmap_seg_iram0_14_end = ALIGN(0x8);
365  } >iram0_14_seg :iram0_14_phdr
366
367  .UserExceptionVector.literal : ALIGN(4)
368  {
369    _UserExceptionVector_literal_start = ABSOLUTE(.);
370    *(.UserExceptionVector.literal)
371    _UserExceptionVector_literal_end = ABSOLUTE(.);
372    _memmap_seg_iram0_15_end = ALIGN(0x8);
373  } >iram0_15_seg :iram0_15_phdr
374
375  .UserExceptionVector.text : ALIGN(4)
376  {
377    _UserExceptionVector_text_start = ABSOLUTE(.);
378    KEEP (*(.UserExceptionVector.text))
379    _UserExceptionVector_text_end = ABSOLUTE(.);
380    _memmap_seg_iram0_16_end = ALIGN(0x8);
381  } >iram0_16_seg :iram0_16_phdr
382
383  .DoubleExceptionVector.literal : ALIGN(4)
384  {
385    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
386    *(.DoubleExceptionVector.literal)
387    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
388    _memmap_seg_iram0_17_end = ALIGN(0x8);
389  } >iram0_17_seg :iram0_17_phdr
390
391  .DoubleExceptionVector.text : ALIGN(4)
392  {
393    _DoubleExceptionVector_text_start = ABSOLUTE(.);
394    KEEP (*(.DoubleExceptionVector.text))
395    _DoubleExceptionVector_text_end = ABSOLUTE(.);
396    _memmap_seg_iram0_18_end = ALIGN(0x8);
397  } >iram0_18_seg :iram0_18_phdr
398
399  .iram0.text : ALIGN(4)
400  {
401    _iram0_text_start = ABSOLUTE(.);
402    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
403    _iram0_text_end = ABSOLUTE(.);
404    _memmap_seg_iram0_19_end = ALIGN(0x8);
405  } >iram0_19_seg :iram0_19_phdr
406
407  .ResetVector.text : ALIGN(4)
408  {
409    __rom_region_start = ABSOLUTE(.);
410    _ResetVector_text_start = ABSOLUTE(.);
411    KEEP (*(.ResetVector.text))
412    _ResetVector_text_end = ABSOLUTE(.);
413    _memmap_seg_srom0_end = ALIGN(0x8);
414  } >srom0_seg :srom0_phdr
415
416#ifdef CONFIG_CODE_DATA_RELOCATION
417#include <linker_relocate.ld>
418#endif
419
420  .srom.rodata : ALIGN(4)
421  {
422    _srom_rodata_start = ABSOLUTE(.);
423    *(.srom.rodata)
424    _srom_rodata_end = ABSOLUTE(.);
425  } >srom1_seg :srom1_phdr
426
427  .srom.text : ALIGN(4)
428  {
429    _srom_text_start = ABSOLUTE(.);
430    *(.srom.literal .srom.text)
431    _srom_text_end = ABSOLUTE(.);
432    _memmap_seg_srom1_end = ALIGN(0x8);
433    __rom_region_end = ABSOLUTE(.);
434  } >srom1_seg :srom1_phdr
435
436  .sram.rodata : ALIGN(4)
437  {
438    _image_ram_start = ABSOLUTE(.);
439    _sram_rodata_start = ABSOLUTE(.);
440    *(.sram.rodata)
441    _sram_rodata_end = ABSOLUTE(.);
442  } >RAM :sram0_phdr
443
444#include <zephyr/linker/common-rom.ld>
445/* Located in generated directory. This file is populated by calling
446 * zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs.
447 */
448#include <snippets-rom-sections.ld>
449
450  .rodata : ALIGN(4)
451  {
452    __rodata_region_start = ABSOLUTE(.);
453    *(.rodata)
454    *(.rodata.*)
455    *(.gnu.linkonce.r.*)
456    *(.rodata1)
457
458    . = ALIGN(4);
459    #include <snippets-rodata.ld>
460    . = ALIGN(4);
461
462    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
463    KEEP (*(.xt_except_table))
464    KEEP (*(.gcc_except_table .gcc_except_table.*))
465    *(.gnu.linkonce.e.*)
466    *(.gnu.version_r)
467    KEEP (*(.eh_frame))
468    /*  C++ constructor and destructor tables, properly ordered:  */
469    KEEP (*crtbegin.o(.ctors))
470    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
471    KEEP (*(SORT(.ctors.*)))
472    KEEP (*(.ctors))
473    KEEP (*crtbegin.o(.dtors))
474    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
475    KEEP (*(SORT(.dtors.*)))
476    KEEP (*(.dtors))
477    /*  C++ exception handlers table:  */
478    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
479    *(.xt_except_desc)
480    *(.gnu.linkonce.h.*)
481    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
482    *(.xt_except_desc_end)
483    *(.dynamic)
484    *(.gnu.version_d)
485    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
486    _bss_table_start = ABSOLUTE(.);
487    LONG(_dram1_bss_start)
488    LONG(_dram1_bss_end)
489    LONG(_dram0_bss_start)
490    LONG(_dram0_bss_end)
491    LONG(_bss_start)
492    LONG(_bss_end)
493    _bss_table_end = ABSOLUTE(.);
494    __rodata_region_end = ABSOLUTE(.);
495  } >RAM :sram0_phdr
496
497  .sram.text : ALIGN(4)
498  {
499    _sram_text_start = ABSOLUTE(.);
500    *(.sram.literal .sram.text)
501    _sram_text_end = ABSOLUTE(.);
502  } >RAM :sram0_phdr
503
504  __text_region_start =  ALIGN(4);
505  .text : ALIGN(4)
506  {
507    _stext = .;
508    _text_start = ABSOLUTE(.);
509    *(.entry.text)
510    *(.init.literal)
511    KEEP(*(.init))
512    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
513    *(.fini.literal)
514    KEEP(*(.fini))
515    *(.gnu.version)
516    _text_end = ABSOLUTE(.);
517    _etext = .;
518  } >RAM :sram0_phdr
519  __text_region_end = .;
520
521  .sram.data : ALIGN(4)
522  {
523    _sram_data_start = ABSOLUTE(.);
524    *(.sram.data)
525    _sram_data_end = ABSOLUTE(.);
526  } >RAM :sram0_phdr
527
528  .noinit :  ALIGN(4)
529  {
530    *(.noinit)
531    *(.noinit.*)
532  } >RAM :sram0_phdr
533
534#include <snippets-sections.ld>
535
536  .data : ALIGN(4)
537  {
538    __data_start = ABSOLUTE(.);
539    *(.data)
540    *(.data.*)
541    *(.gnu.linkonce.d.*)
542    KEEP(*(.gnu.linkonce.d.*personality*))
543    *(.data1)
544    *(.sdata)
545    *(.sdata.*)
546    *(.gnu.linkonce.s.*)
547    *(.sdata2)
548    *(.sdata2.*)
549    *(.gnu.linkonce.s2.*)
550    KEEP(*(.jcr))
551
552    . = ALIGN(4);
553    #include <snippets-rwdata.ld>
554    . = ALIGN(4);
555
556#ifdef CONFIG_CODE_DATA_RELOCATION
557#include <linker_sram_data_relocate.ld>
558#endif
559    . = ALIGN(4);
560
561    __data_end = ABSOLUTE(.);
562  } >RAM :sram0_phdr
563
564#include <snippets-data-sections.ld>
565
566#include <zephyr/linker/common-ram.ld>
567
568  .tm_clone_table :
569  {
570    *(.tm_clone_table)
571  } >RAM :sram0_phdr
572
573#include <snippets-ram-sections.ld>
574
575  .bss (NOLOAD) : ALIGN(8)
576  {
577    . = ALIGN (8);
578    _bss_start = ABSOLUTE(.);
579    *(.dynsbss)
580    *(.sbss)
581    *(.sbss.*)
582    *(.gnu.linkonce.sb.*)
583    *(.scommon)
584    *(.sbss2)
585    *(.sbss2.*)
586    *(.gnu.linkonce.sb2.*)
587    *(.dynbss)
588    *(.bss)
589    *(.bss.*)
590    *(.gnu.linkonce.b.*)
591    *(COMMON)
592    *(.sram.bss)
593#ifdef CONFIG_CODE_DATA_RELOCATION
594#include <linker_sram_bss_relocate.ld>
595#endif
596    . = ALIGN (8);
597    _bss_end = ABSOLUTE(.);
598    _end = ALIGN(0x8);
599    _image_ram_end = ABSOLUTE(.);
600    PROVIDE(end = ALIGN(0x8));
601    _stack_sentry = ALIGN(0x8);
602    _memmap_seg_sram0_end = ALIGN(0x8);
603  } >RAM :sram0_bss_phdr
604  __stack = 0x64000000;
605  _heap_sentry = 0x64000000;
606  .comment  0 :  { *(.comment) }
607  .debug  0 :  { *(.debug) }
608  .line  0 :  { *(.line) }
609  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
610  .debug_sfnames  0 :  { *(.debug_sfnames) }
611  .debug_aranges  0 :  { *(.debug_aranges) }
612  .debug_pubnames  0 :  { *(.debug_pubnames) }
613  .debug_info  0 :  { *(.debug_info) }
614  .debug_abbrev  0 :  { *(.debug_abbrev) }
615  .debug_line  0 :  { *(.debug_line) }
616  .debug_frame  0 :  { *(.debug_frame) }
617  .debug_str  0 :  { *(.debug_str) }
618  .debug_loc  0 :  { *(.debug_loc) }
619  .debug_macinfo  0 :  { *(.debug_macinfo) }
620  .debug_weaknames  0 :  { *(.debug_weaknames) }
621  .debug_funcnames  0 :  { *(.debug_funcnames) }
622  .debug_typenames  0 :  { *(.debug_typenames) }
623  .debug_varnames  0 :  { *(.debug_varnames) }
624  .debug_ranges  0 :  { *(.debug_ranges) }
625  .debug_addr  0 :  { *(.debug_addr) }
626  .debug_line_str  0 :  { *(.debug_line_str) }
627  .debug_loclists  0 :  { *(.debug_loclists) }
628  .debug_macro  0 :  { *(.debug_macro) }
629  .debug_names  0 :  { *(.debug_names) }
630  .debug_rnglists  0 :  { *(.debug_rnglists) }
631  .debug_str_offsets  0 :  { *(.debug_str_offsets) }
632  .debug_sup  0 :  { *(.debug_sup) }
633  .xtensa.info  0 :  { *(.xtensa.info) }
634  .xt.insn 0 :
635  {
636    KEEP (*(.xt.insn))
637    KEEP (*(.gnu.linkonce.x.*))
638  }
639  .xt.prop 0 :
640  {
641    KEEP (*(.xt.prop))
642    KEEP (*(.xt.prop.*))
643    KEEP (*(.gnu.linkonce.prop.*))
644  }
645  .xt.lit 0 :
646  {
647    KEEP (*(.xt.lit))
648    KEEP (*(.xt.lit.*))
649    KEEP (*(.gnu.linkonce.p.*))
650  }
651  .debug.xt.callgraph 0 :
652  {
653    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
654  }
655
656  /DISCARD/ : { *(.note.GNU-stack) }
657}
658