1 /*
2 * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT microchip_sam_pit64b
8
9 #include <zephyr/arch/cpu.h>
10 #include <zephyr/drivers/timer/system_timer.h>
11 #include <zephyr/init.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/logging/log.h>
14 #include <zephyr/spinlock.h>
15 #include <zephyr/sys_clock.h>
16
17 LOG_MODULE_REGISTER(pit64b, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
18
19 /* Device constant configuration parameters */
20 struct sam_pit64b_cfg {
21 pit64b_registers_t *reg;
22 };
23
24 #define CYCLES_PER_TICK (sys_clock_hw_cycles_per_sec() / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
25
26 #define MAX_TICKS ((k_ticks_t)(0x1FFFFF / CYCLES_PER_TICK) - 1)
27 #define MIN_DELAY MAX(1024U, ((uint32_t)CYCLES_PER_TICK/16U))
28 #define MAX_CYCLES (MAX_TICKS * CYCLES_PER_TICK)
29
30 typedef uint32_t cycle_t;
31
32 static struct k_spinlock lock;
33
34 static cycle_t announced_cycles;
35 static cycle_t cycle_count;
36 static uint32_t last_load;
37 static uint32_t overflow;
38
39 const int32_t z_sys_timer_irq_for_test = DT_INST_IRQN(0);
40
41 const static struct sam_pit64b_cfg pit64b_cfg = {
42 .reg = (pit64b_registers_t *)DT_INST_REG_ADDR(0),
43 };
44
cycles_elapsed(void)45 static uint32_t cycles_elapsed(void)
46 {
47 uint32_t val1 = pit64b_cfg.reg->PIT64B_TLSBR;
48 uint32_t ctrl = pit64b_cfg.reg->PIT64B_ISR;
49 uint32_t val2 = pit64b_cfg.reg->PIT64B_TLSBR;
50
51 if ((ctrl & PIT64B_IER_PERIOD_Msk) || (val1 > val2)) {
52 overflow += last_load;
53 (void)PIT64B0_REGS->PIT64B_TLSBR;
54 }
55
56 return val2 + overflow;
57 }
58
pit64b_isr(const void * arg)59 static void pit64b_isr(const void *arg)
60 {
61 ARG_UNUSED(arg);
62
63 uint32_t dcycles;
64 uint32_t delta_ticks;
65
66 (void)cycles_elapsed();
67
68 if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
69 cycle_count += overflow;
70 overflow = 0;
71
72 dcycles = cycle_count - announced_cycles;
73 delta_ticks = dcycles / CYCLES_PER_TICK;
74 announced_cycles += delta_ticks * CYCLES_PER_TICK;
75
76 sys_clock_announce(delta_ticks);
77 } else {
78 sys_clock_announce(1);
79 }
80 }
81
sys_clock_set_timeout(int32_t ticks,bool idle)82 void sys_clock_set_timeout(int32_t ticks, bool idle)
83 {
84 ARG_UNUSED(idle);
85
86 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
87 return;
88 }
89
90 uint32_t tmp = last_load;
91 k_spinlock_key_t key;
92 int32_t unannounced;
93 uint32_t val1, val2;
94 uint32_t delay;
95
96 ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
97
98 key = k_spin_lock(&lock);
99 cycle_count += cycles_elapsed();
100 overflow = 0;
101
102 val1 = pit64b_cfg.reg->PIT64B_TLSBR;
103
104 unannounced = cycle_count - announced_cycles;
105 if (unannounced < 0) {
106 last_load = MIN_DELAY;
107 } else {
108 delay = ticks * CYCLES_PER_TICK;
109 delay += unannounced;
110 delay = DIV_ROUND_UP(delay, CYCLES_PER_TICK) * CYCLES_PER_TICK;
111 delay -= unannounced;
112 delay = MAX(delay, MIN_DELAY);
113 if (delay > MAX_CYCLES) {
114 last_load = MAX_CYCLES;
115 } else {
116 last_load = delay;
117 }
118 }
119
120 val2 = pit64b_cfg.reg->PIT64B_TLSBR;
121
122 pit64b_cfg.reg->PIT64B_LSBPR = last_load;
123
124 if (val1 > val2) {
125 cycle_count += (val2 + (tmp - val1));
126 } else {
127 cycle_count += (val2 - val1);
128 }
129
130 k_spin_unlock(&lock, key);
131 }
132
sys_clock_elapsed(void)133 uint32_t sys_clock_elapsed(void)
134 {
135 uint32_t cycles;
136
137 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
138 return 0;
139 }
140
141 k_spinlock_key_t key = k_spin_lock(&lock);
142
143 cycles = cycles_elapsed();
144
145 k_spin_unlock(&lock, key);
146
147 return (cycles + cycle_count - announced_cycles) / CYCLES_PER_TICK;
148 }
149
sys_clock_cycle_get_32(void)150 uint32_t sys_clock_cycle_get_32(void)
151 {
152 k_spinlock_key_t key = k_spin_lock(&lock);
153
154 uint32_t cycles = cycles_elapsed();
155
156 k_spin_unlock(&lock, key);
157
158 return cycle_count + cycles;
159 }
160
sys_clock_cycle_get_64(void)161 uint64_t sys_clock_cycle_get_64(void)
162 {
163 k_spinlock_key_t key = k_spin_lock(&lock);
164
165 uint64_t cycles = cycles_elapsed();
166
167 k_spin_unlock(&lock, key);
168
169 return cycle_count + cycles;
170 }
171
sys_clock_driver_init(void)172 static int sys_clock_driver_init(void)
173 {
174 pit64b_cfg.reg->PIT64B_CR |= PIT64B_CR_SWRST_Msk;
175
176 pit64b_cfg.reg->PIT64B_IER |= PIT64B_IER_PERIOD_Msk;
177 pit64b_cfg.reg->PIT64B_MR = PIT64B_MR_CONT_Msk | PIT64B_MR_SMOD_Msk |
178 PIT64B_MR_SGCLK_Msk | PIT64B_MR_PRESCALER(1 - 1);
179
180 last_load = CYCLES_PER_TICK;
181 announced_cycles = 0;
182 cycle_count = 0;
183 overflow = 0;
184 pit64b_cfg.reg->PIT64B_MSBPR = 0;
185 pit64b_cfg.reg->PIT64B_LSBPR = last_load;
186 pit64b_cfg.reg->PIT64B_CR |= PIT64B_CR_START_Msk;
187
188 IRQ_CONNECT(DT_INST_IRQN(0), 0, pit64b_isr, 0, 0);
189 irq_enable(DT_INST_IRQN(0));
190
191 return 0;
192 }
193
194 SYS_INIT(sys_clock_driver_init, POST_KERNEL, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
195
