1 /*
2 * Copyright (c) Carlo Caione <ccaione@baylibre.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT syscon
8
9 #include <errno.h>
10
11 #include <zephyr/arch/cpu.h>
12 #include <zephyr/sys/util.h>
13 #include <zephyr/device.h>
14 #include <zephyr/init.h>
15
16 #include <zephyr/drivers/syscon.h>
17
18 #include "syscon_common.h"
19
20 struct syscon_generic_config {
21 DEVICE_MMIO_ROM;
22 uint8_t reg_width;
23 };
24
25 struct syscon_generic_data {
26 DEVICE_MMIO_RAM;
27 size_t size;
28 };
29
syscon_generic_get_base(const struct device * dev,uintptr_t * addr)30 static int syscon_generic_get_base(const struct device *dev, uintptr_t *addr)
31 {
32 *addr = DEVICE_MMIO_GET(dev);
33 return 0;
34 }
35
syscon_generic_read_reg(const struct device * dev,uint16_t reg,uint32_t * val)36 static int syscon_generic_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
37 {
38 const struct syscon_generic_config *config = dev->config;
39 struct syscon_generic_data *data = dev->data;
40 uintptr_t base_address;
41
42 if (!val) {
43 return -EINVAL;
44 }
45
46 if (syscon_sanitize_reg(®, data->size, config->reg_width)) {
47 return -EINVAL;
48 }
49
50 base_address = DEVICE_MMIO_GET(dev);
51
52 switch (config->reg_width) {
53 case 1:
54 *val = sys_read8(base_address + reg);
55 break;
56 case 2:
57 *val = sys_read16(base_address + reg);
58 break;
59 case 4:
60 *val = sys_read32(base_address + reg);
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 return 0;
67 }
68
syscon_generic_write_reg(const struct device * dev,uint16_t reg,uint32_t val)69 static int syscon_generic_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
70 {
71 const struct syscon_generic_config *config = dev->config;
72 struct syscon_generic_data *data = dev->data;
73 uintptr_t base_address;
74
75 if (syscon_sanitize_reg(®, data->size, config->reg_width)) {
76 return -EINVAL;
77 }
78
79 base_address = DEVICE_MMIO_GET(dev);
80
81 switch (config->reg_width) {
82 case 1:
83 sys_write8(val, (base_address + reg));
84 break;
85 case 2:
86 sys_write16(val, (base_address + reg));
87 break;
88 case 4:
89 sys_write32(val, (base_address + reg));
90 break;
91 default:
92 return -EINVAL;
93 }
94
95 return 0;
96 }
97
syscon_generic_get_size(const struct device * dev,size_t * size)98 static int syscon_generic_get_size(const struct device *dev, size_t *size)
99 {
100 struct syscon_generic_data *data = dev->data;
101
102 *size = data->size;
103 return 0;
104 }
105
106 static DEVICE_API(syscon, syscon_generic_driver_api) = {
107 .read = syscon_generic_read_reg,
108 .write = syscon_generic_write_reg,
109 .get_base = syscon_generic_get_base,
110 .get_size = syscon_generic_get_size,
111 };
112
syscon_generic_init(const struct device * dev)113 static int syscon_generic_init(const struct device *dev)
114 {
115 DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
116
117 return 0;
118 }
119
120 #define SYSCON_INIT(inst) \
121 static const struct syscon_generic_config syscon_generic_config_##inst = { \
122 DEVICE_MMIO_ROM_INIT(DT_DRV_INST(inst)), \
123 .reg_width = DT_INST_PROP_OR(inst, reg_io_width, 4), \
124 }; \
125 static struct syscon_generic_data syscon_generic_data_##inst = { \
126 .size = DT_INST_REG_SIZE(inst), \
127 }; \
128 DEVICE_DT_INST_DEFINE(inst, syscon_generic_init, NULL, &syscon_generic_data_##inst, \
129 &syscon_generic_config_##inst, PRE_KERNEL_1, \
130 CONFIG_SYSCON_INIT_PRIORITY, &syscon_generic_driver_api);
131
132 DT_INST_FOREACH_STATUS_OKAY(SYSCON_INIT);
133
