1 /* 2 * Copyright (c) 2013-2014 Wind River Systems, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief Stack helpers for Cortex-M CPUs 10 * 11 * Stack helper functions. 12 */ 13 14 #ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_STACK_H_ 15 #define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_STACK_H_ 16 17 #ifdef _ASMLANGUAGE 18 19 /* nothing */ 20 21 #else 22 23 #include <cmsis_core.h> 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, CONFIG_ISR_STACK_SIZE); 30 31 /** 32 * 33 * @brief Setup interrupt stack 34 * 35 * On Cortex-M, the interrupt stack is registered in the MSP (main stack 36 * pointer) register, and switched to automatically when taking an exception. 37 * 38 */ z_arm_interrupt_stack_setup(void)39static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void) 40 { 41 uint32_t msp = (uint32_t)(K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) + 42 K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]); 43 44 __set_MSP(msp); 45 #if defined(CONFIG_BUILTIN_STACK_GUARD) 46 #if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM) 47 __set_MSPLIM((uint32_t)z_interrupt_stacks[0]); 48 #else 49 #error "Built-in MSP limit checks not supported by HW" 50 #endif 51 #endif /* CONFIG_BUILTIN_STACK_GUARD */ 52 53 #if defined(CONFIG_STACK_ALIGN_DOUBLE_WORD) 54 /* Enforce double-word stack alignment on exception entry 55 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest 56 * of ARM Cortex-M processors this setting is enforced by 57 * default and it is not configurable. 58 */ 59 #if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4) 60 SCB->CCR |= SCB_CCR_STKALIGN_Msk; 61 #endif 62 #endif /* CONFIG_STACK_ALIGN_DOUBLE_WORD */ 63 } 64 65 #ifdef __cplusplus 66 } 67 #endif 68 69 #endif /* _ASMLANGUAGE */ 70 71 #endif /* ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_STACK_H_ */ 72
