1/*
2 * Copyright (c) 2019 - 2020 Nordic Semiconductor ASA
3 * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#if defined(CONFIG_CPU_CORTEX_M_HAS_VTOR)
9/*
10 * In an MCU with VTOR, the VTOR.TBLOFF is set to the start address of the
11 * exc_vector_table (i.e. _vector_start) during initialization. Therefore,
12 * exc_vector_table must respect the alignment requirements of VTOR.TBLOFF
13 * described below.
14 */
15
16#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
17/* VTOR bits 0:7 are reserved (RES0). This requires that the base address
18 * of the vector table is 64-word aligned.
19 */
20. = ALIGN( 1 << LOG2CEIL(4 * 64) );
21#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
22/* VTOR bits 0:6 are reserved (RES0). This requires that the base address
23 * of the vector table is 32-word aligned.
24 */
25. = ALIGN( 1 << LOG2CEIL(4 * 32) );
26#else
27#error "Unsupported architecture variant"
28#endif
29
30/* When setting TBLOFF in VTOR we must align the offset to the number of
31 * exception entries in the vector table. The minimum alignment of 32 words
32 * is sufficient for the 16 ARM Core exceptions and up to 16 HW interrupts.
33 * For more than 16 HW interrupts, we adjust the alignment by rounding up
34 * to the next power of two; this restriction guarantees a functional VTOR
35 * setting in any Cortex-M implementation (might not be required in every
36 * Cortex-M processor).
37 */
38. = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) );
39#endif
40
41#ifdef CONFIG_ARM_ZIMAGE_HEADER
42/*
43 * For AArch32 (A/R), VBAR has Bits [4:0] = RES0.
44 * For AArch32 (M), VTOR has Bits [6:0] = RES0. Thus, vector start address
45 * should be aligned in such a way so that it satisfies the requirements of
46 * VBAR and VTOR ie Bits [6:0] = 0.
47 */
48. = ALIGN( 0x80 );
49#endif
50
51_vector_start = .;
52KEEP(*(.exc_vector_table))
53KEEP(*(".exc_vector_table.*"))
54
55#if LINKER_ZEPHYR_FINAL && defined(CONFIG_ISR_TABLES_LOCAL_DECLARATION)
56INCLUDE isr_tables_vt.ld
57#else
58KEEP(*(.vectors))
59#endif
60
61#ifdef CONFIG_CPU_AARCH32_CORTEX_R
62KEEP(*(._bindesc_entry.*))
63#endif
64
65_vector_end = .;
66