1 /*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /*
8 * Based on DMIC driver sample, which is:
9 * Copyright (c) 2021 Nordic Semiconductor ASA
10 */
11
12 #include <zephyr/kernel.h>
13 #include <zephyr/audio/dmic.h>
14 #include <zephyr/ztest.h>
15
16 static const struct device *dmic_dev = DEVICE_DT_GET(DT_ALIAS(dmic_dev));
17
18 #if DT_HAS_COMPAT_STATUS_OKAY(nxp_dmic)
19 #define PDM_CHANNELS 4 /* Two L/R pairs of channels */
20 #define SAMPLE_BIT_WIDTH 16
21 #define BYTES_PER_SAMPLE sizeof(int16_t)
22 #define SLAB_ALIGN 4
23 #define MAX_SAMPLE_RATE 48000
24 #elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pdm)
25 #define PDM_CHANNELS 2
26 #define SAMPLE_BIT_WIDTH 16
27 #define BYTES_PER_SAMPLE sizeof(int16_t)
28 #define SLAB_ALIGN 4
29 #define MAX_SAMPLE_RATE 48000
30 #else
31 #error "Unsupported DMIC device"
32 #endif
33
34 /* Milliseconds to wait for a block to be read. */
35 #define READ_TIMEOUT 1000
36 /* Size of a block for 100 ms of audio data. */
37 #define BLOCK_SIZE(_sample_rate, _number_of_channels) \
38 (BYTES_PER_SAMPLE * (_sample_rate / 10) * _number_of_channels)
39
40 /* Driver will allocate blocks from this slab to receive audio data into them.
41 * Application, after getting a given block from the driver and processing its
42 * data, needs to free that block.
43 */
44 #define MAX_BLOCK_SIZE BLOCK_SIZE(MAX_SAMPLE_RATE, PDM_CHANNELS)
45 #define BLOCK_COUNT 8
46 K_MEM_SLAB_DEFINE_STATIC(mem_slab, MAX_BLOCK_SIZE, BLOCK_COUNT, SLAB_ALIGN);
47
48 static struct pcm_stream_cfg pcm_stream = {
49 .pcm_width = SAMPLE_BIT_WIDTH,
50 .mem_slab = &mem_slab,
51 };
52 static struct dmic_cfg dmic_cfg = {
53 .io = {
54 /* These fields can be used to limit the PDM clock
55 * configurations that the driver is allowed to use
56 * to those supported by the microphone.
57 */
58 .min_pdm_clk_freq = 1000000,
59 .max_pdm_clk_freq = 3500000,
60 .min_pdm_clk_dc = 40,
61 .max_pdm_clk_dc = 60,
62 },
63 .streams = &pcm_stream,
64 .channel = {
65 .req_num_streams = 1,
66 },
67 };
68
69 /* Verify that dmic_trigger fails when DMIC is not configured
70 * this test must run first, before DMIC has been configured
71 */
ZTEST(dmic,test_0_start_fail)72 ZTEST(dmic, test_0_start_fail)
73 {
74 int ret;
75
76 zassert_true(device_is_ready(dmic_dev), "DMIC device is not ready");
77 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_START);
78 zassert_not_equal(ret, 0, "DMIC trigger should fail when DMIC is not configured");
79 }
80
do_pdm_transfer(const struct device * dmic,struct dmic_cfg * cfg)81 static int do_pdm_transfer(const struct device *dmic,
82 struct dmic_cfg *cfg)
83 {
84 int ret;
85 void *buffer;
86 uint32_t size;
87
88 TC_PRINT("PCM output rate: %u, channels: %u\n",
89 cfg->streams[0].pcm_rate, cfg->channel.req_num_chan);
90
91 ret = dmic_configure(dmic, cfg);
92 if (ret < 0) {
93 TC_PRINT("DMIC configuration failed: %d\n", ret);
94 return ret;
95 }
96
97 /* Check that the driver is properly populating the "act*" fields */
98 zassert_equal(cfg->channel.act_num_chan,
99 cfg->channel.req_num_chan,
100 "DMIC configure should populate act_num_chan field");
101 zassert_equal(cfg->channel.act_chan_map_lo,
102 cfg->channel.req_chan_map_lo,
103 "DMIC configure should populate act_chan_map_lo field");
104 zassert_equal(cfg->channel.act_chan_map_hi,
105 cfg->channel.req_chan_map_hi,
106 "DMIC configure should populate act_chan_map_hi field");
107 ret = dmic_trigger(dmic, DMIC_TRIGGER_START);
108 if (ret < 0) {
109 TC_PRINT("DMIC start trigger failed: %d\n", ret);
110 return ret;
111 }
112
113 /* We read more than the total BLOCK_COUNT to insure the DMIC
114 * driver correctly reallocates memory slabs as it exhausts existing
115 * ones.
116 */
117 for (int i = 0; i < (2 * BLOCK_COUNT); i++) {
118 ret = dmic_read(dmic, 0, &buffer, &size, READ_TIMEOUT);
119 if (ret < 0) {
120 TC_PRINT("DMIC read failed: %d\n", ret);
121 return ret;
122 }
123
124 TC_PRINT("%d - got buffer %p of %u bytes\n", i, buffer, size);
125 k_mem_slab_free(&mem_slab, buffer);
126 }
127
128 ret = dmic_trigger(dmic, DMIC_TRIGGER_STOP);
129 if (ret < 0) {
130 TC_PRINT("DMIC stop trigger failed: %d\n", ret);
131 return ret;
132 }
133 return 0;
134 }
135
136
137 /* Verify that the DMIC can transfer from a single channel */
ZTEST(dmic,test_single_channel)138 ZTEST(dmic, test_single_channel)
139 {
140 dmic_cfg.channel.req_num_chan = 1;
141 dmic_cfg.channel.req_chan_map_lo =
142 dmic_build_channel_map(0, 0, PDM_CHAN_LEFT);
143 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
144 dmic_cfg.streams[0].block_size =
145 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
146 dmic_cfg.channel.req_num_chan);
147 zassert_equal(do_pdm_transfer(dmic_dev, &dmic_cfg), 0,
148 "Single channel transfer failed");
149 }
150
151 /* Verify that the DMIC can transfer from a L/R channel pair */
ZTEST(dmic,test_stereo_channel)152 ZTEST(dmic, test_stereo_channel)
153 {
154 dmic_cfg.channel.req_num_chan = 2;
155 dmic_cfg.channel.req_chan_map_lo =
156 dmic_build_channel_map(0, 0, PDM_CHAN_LEFT) |
157 dmic_build_channel_map(1, 0, PDM_CHAN_RIGHT);
158 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
159 dmic_cfg.streams[0].block_size =
160 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
161 dmic_cfg.channel.req_num_chan);
162 zassert_equal(do_pdm_transfer(dmic_dev, &dmic_cfg), 0,
163 "L/R channel transfer failed");
164 dmic_cfg.channel.req_chan_map_lo =
165 dmic_build_channel_map(0, 0, PDM_CHAN_RIGHT) |
166 dmic_build_channel_map(1, 0, PDM_CHAN_LEFT);
167 zassert_equal(do_pdm_transfer(dmic_dev, &dmic_cfg), 0,
168 "R/L channel transfer failed");
169 }
170
171 /* Test DMIC with maximum number of channels */
ZTEST(dmic,test_max_channel)172 ZTEST(dmic, test_max_channel)
173 {
174 enum pdm_lr lr;
175 uint8_t pdm_hw_chan;
176
177 dmic_cfg.channel.req_num_chan = PDM_CHANNELS;
178 dmic_cfg.channel.req_chan_map_lo = 0;
179 dmic_cfg.channel.req_chan_map_hi = 0;
180 for (uint8_t i = 0; i < PDM_CHANNELS; i++) {
181 lr = ((i % 2) == 0) ? PDM_CHAN_LEFT : PDM_CHAN_RIGHT;
182 pdm_hw_chan = i >> 1;
183 if (i < 4) {
184 dmic_cfg.channel.req_chan_map_lo |=
185 dmic_build_channel_map(i, pdm_hw_chan, lr);
186 } else {
187 dmic_cfg.channel.req_chan_map_hi |=
188 dmic_build_channel_map(i, pdm_hw_chan, lr);
189 }
190 }
191
192 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
193 dmic_cfg.streams[0].block_size =
194 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
195 dmic_cfg.channel.req_num_chan);
196 zassert_equal(do_pdm_transfer(dmic_dev, &dmic_cfg), 0,
197 "Maximum channel transfer failed");
198 }
199
200 /* Test pausing and restarting a channel */
ZTEST(dmic,test_pause_restart)201 ZTEST(dmic, test_pause_restart)
202 {
203 int ret, i;
204 void *buffer;
205 uint32_t size;
206
207 dmic_cfg.channel.req_num_chan = 1;
208 dmic_cfg.channel.req_chan_map_lo =
209 dmic_build_channel_map(0, 0, PDM_CHAN_LEFT);
210 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
211 dmic_cfg.streams[0].block_size =
212 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
213 dmic_cfg.channel.req_num_chan);
214 ret = dmic_configure(dmic_dev, &dmic_cfg);
215 zassert_equal(ret, 0, "DMIC configure failed");
216
217 /* Start the DMIC, and pause it immediately */
218 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_START);
219 zassert_equal(ret, 0, "DMIC start failed");
220 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_PAUSE);
221 zassert_equal(ret, 0, "DMIC pause failed");
222 /* There may be some buffers in the DMIC queue, but a read
223 * should eventually time out while it is paused
224 */
225 for (i = 0; i < (2 * BLOCK_COUNT); i++) {
226 ret = dmic_read(dmic_dev, 0, &buffer, &size, READ_TIMEOUT);
227 if (ret < 0) {
228 break;
229 }
230 k_mem_slab_free(&mem_slab, buffer);
231 }
232 zassert_not_equal(ret, 0, "DMIC is paused, reads should timeout");
233 TC_PRINT("Queue drained after %d reads\n", i);
234 /* Unpause the DMIC */
235 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_RELEASE);
236 zassert_equal(ret, 0, "DMIC release failed");
237 /* Reads should not timeout now */
238 for (i = 0; i < (2 * BLOCK_COUNT); i++) {
239 ret = dmic_read(dmic_dev, 0, &buffer, &size, READ_TIMEOUT);
240 if (ret < 0) {
241 break;
242 }
243 k_mem_slab_free(&mem_slab, buffer);
244 }
245 zassert_equal(ret, 0, "DMIC is active, reads should succeed");
246 TC_PRINT("%d reads completed\n", (2 * BLOCK_COUNT));
247 /* Stop the DMIC, and repeat the same tests */
248 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_STOP);
249 zassert_equal(ret, 0, "DMIC stop failed");
250 /* Versus a pause, DMIC reads should immediately stop once DMIC times
251 * out
252 */
253 ret = dmic_read(dmic_dev, 0, &buffer, &size, READ_TIMEOUT);
254 zassert_not_equal(ret, 0, "DMIC read should timeout when DMIC is stopped");
255 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_START);
256 zassert_equal(ret, 0, "DMIC restart failed");
257 /* Reads should not timeout now */
258 for (i = 0; i < (2 * BLOCK_COUNT); i++) {
259 ret = dmic_read(dmic_dev, 0, &buffer, &size, READ_TIMEOUT);
260 if (ret < 0) {
261 break;
262 }
263 k_mem_slab_free(&mem_slab, buffer);
264 }
265 zassert_equal(ret, 0, "DMIC is active, reads should succeed");
266 TC_PRINT("%d reads completed\n", (2 * BLOCK_COUNT));
267 /* Test is over. Stop the DMIC */
268 ret = dmic_trigger(dmic_dev, DMIC_TRIGGER_STOP);
269 zassert_equal(ret, 0, "DMIC stop failed");
270 }
271
272 /* Verify that channel map without adjacent L/R pairs fails */
ZTEST(dmic,test_bad_pair)273 ZTEST(dmic, test_bad_pair)
274 {
275 int ret;
276
277 dmic_cfg.channel.req_num_chan = 2;
278 dmic_cfg.channel.req_chan_map_lo =
279 dmic_build_channel_map(0, 0, PDM_CHAN_RIGHT) |
280 dmic_build_channel_map(1, 0, PDM_CHAN_RIGHT);
281 dmic_cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
282 dmic_cfg.streams[0].block_size =
283 BLOCK_SIZE(dmic_cfg.streams[0].pcm_rate,
284 dmic_cfg.channel.req_num_chan);
285 ret = dmic_configure(dmic_dev, &dmic_cfg);
286 zassert_not_equal(ret, 0, "DMIC configure should fail with "
287 "two of same channel in map");
288
289 dmic_cfg.channel.req_num_chan = 2;
290 dmic_cfg.channel.req_chan_map_lo =
291 dmic_build_channel_map(0, 0, PDM_CHAN_RIGHT) |
292 dmic_build_channel_map(1, 1, PDM_CHAN_LEFT);
293 ret = dmic_configure(dmic_dev, &dmic_cfg);
294 zassert_not_equal(ret, 0, "DMIC configure should fail with "
295 "non adjacent channels in map");
296 }
297
298 ZTEST_SUITE(dmic, NULL, NULL, NULL, NULL, NULL);
299
