1# Copyright 2022-2024 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4config SOC_SERIES_RW6XX
5	select ARM
6	select CPU_CORTEX_M33
7	select CPU_CORTEX_M_HAS_DWT
8	select CLOCK_CONTROL
9	select SOC_RESET_HOOK
10	select CPU_HAS_ARM_SAU
11	select CPU_HAS_ARM_MPU
12	select CPU_HAS_FPU
13	select HAS_MCUX_OS_TIMER
14	select ARM_TRUSTZONE_M
15	select CPU_CORTEX_M_HAS_SYSTICK
16	select HAS_MCUX
17	select HAS_MCUX_FLEXCOMM
18	select HAS_MCUX_CACHE
19	select HAS_PM
20	select HAS_NXP_MONOLITHIC_NBU
21	select SOC_EARLY_INIT_HOOK
22	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
23
24if SOC_SERIES_RW6XX
25
26menuconfig NXP_RW6XX_BOOT_HEADER
27	bool "Create boot header"
28	default y if !BOOTLOADER_MCUBOOT
29	help
30	  Create data structures required by the boot ROM to boot the
31	  application from an external flash device.
32
33if NXP_RW6XX_BOOT_HEADER
34
35rsource "../common/Kconfig.rom_loader"
36
37config FLASH_CONFIG_OFFSET
38	hex "Flash config data offset"
39	default 0x400
40	help
41	  The flash config offset provides the boot ROM with the on-board
42	  flash type and parameters. The boot ROM requires a fixed flash conifg
43	  offset for FlexSPI device.
44
45config IMAGE_VECTOR_TABLE_OFFSET
46	hex "Image vector table offset"
47	default 0x1000
48	help
49	  The Image Vector Table (IVT) provides the boot ROM with pointers to
50	  the application entry point and device configuration data. The boot
51	  ROM requires a fixed IVT offset for each type of boot device.
52
53endif # NXP_RW6XX_BOOT_HEADER
54
55rsource "../common/Kconfig.flexspi_xip"
56rsource "../common/Kconfig.nbu"
57
58endif # SOC_SERIES_RW6XX
59