1/*
2 * Copyright 2024-2025 NXP
3 * SPDX-License-Identifier: Apache-2.0
4 *
5 */
6
7#include <nxp/nxp_imx/rt/mimxrt1189cvm8b-pinctrl.dtsi>
8
9&pinctrl {
10	emdio_default: emdio_default {
11		group1 {
12			pinmux = <&iomuxc_gpio_ad_30_netc_emdc>,
13				<&iomuxc_gpio_ad_31_netc_emdio>;
14			bias-pull-down;
15			slew-rate = "fast";
16			drive-strength = "high";
17		};
18	};
19
20	eth0_default: eth0_default {
21		group1 {
22			pinmux = <&iomuxc_gpio_emc_b2_05_eth0_tx_data0>,
23				<&iomuxc_gpio_emc_b2_06_eth0_tx_data1>,
24				<&iomuxc_gpio_emc_b2_07_eth0_tx_en>,
25				<&iomuxc_gpio_emc_b2_09_eth0_rx_data0>,
26				<&iomuxc_gpio_emc_b2_10_eth0_rx_data1>,
27				<&iomuxc_gpio_emc_b2_11_eth0_rx_en>,
28				<&iomuxc_gpio_emc_b2_12_eth0_rx_er>;
29			bias-pull-down;
30			slew-rate = "fast";
31			drive-strength = "high";
32		};
33		group2 {
34			pinmux = <&iomuxc_gpio_emc_b2_08_eth0_tx_clk>;
35			input-enable;
36			bias-pull-down;
37			slew-rate = "fast";
38			drive-strength = "high";
39		};
40	};
41
42	eth1_default: eth1_default {
43		group1 {
44			pinmux = <&iomuxc_gpio_b1_00_eth1_tx_data0>,
45				<&iomuxc_gpio_b1_01_eth1_tx_data1>,
46				<&iomuxc_gpio_b1_02_eth1_tx_en>,
47				<&iomuxc_gpio_b1_03_eth1_tx_clk >,
48				<&iomuxc_gpio_b1_04_eth1_rx_data0>,
49				<&iomuxc_gpio_b1_05_eth1_rx_data1>,
50				<&iomuxc_gpio_b1_06_eth1_rx_en>,
51				<&iomuxc_gpio_b1_07_eth1_tx_data2>,
52				<&iomuxc_gpio_b1_08_eth1_tx_data3>,
53				<&iomuxc_gpio_b1_09_eth1_rx_data2>,
54				<&iomuxc_gpio_b1_10_eth1_rx_data3>,
55				<&iomuxc_gpio_b1_11_eth1_rx_clk>;
56			bias-pull-down;
57			slew-rate = "fast";
58			drive-strength = "high";
59		};
60	};
61
62	eth2_default: eth2_default {
63		group1 {
64			pinmux = <&iomuxc_gpio_emc_b1_13_eth2_rx_en>,
65				<&iomuxc_gpio_emc_b1_16_eth2_rx_data0>,
66				<&iomuxc_gpio_emc_b1_17_eth2_rx_data1>,
67				<&iomuxc_gpio_emc_b1_21_eth2_rx_clk>,
68				<&iomuxc_gpio_emc_b1_22_eth2_rx_data2>,
69				<&iomuxc_gpio_emc_b1_23_eth2_rx_data3>,
70				<&iomuxc_gpio_emc_b1_24_eth2_tx_data3>,
71				<&iomuxc_gpio_emc_b1_25_eth2_tx_data2>,
72				<&iomuxc_gpio_emc_b1_26_eth2_tx_data1>,
73				<&iomuxc_gpio_emc_b1_27_eth2_tx_data0>,
74				<&iomuxc_gpio_emc_b1_28_eth2_tx_en>,
75				<&iomuxc_gpio_emc_b1_29_eth2_tx_clk>;
76			bias-pull-down;
77			slew-rate = "fast";
78			drive-strength = "high";
79		};
80	};
81
82	eth3_default: eth3_default {
83		group1 {
84			pinmux = <&iomuxc_gpio_emc_b1_00_eth3_tx_data3>,
85				<&iomuxc_gpio_emc_b1_01_eth3_tx_data2>,
86				<&iomuxc_gpio_emc_b1_02_eth3_rx_clk>,
87				<&iomuxc_gpio_emc_b1_03_eth3_rx_data3>,
88				<&iomuxc_gpio_emc_b1_04_eth3_rx_data2>,
89				<&iomuxc_gpio_emc_b1_05_eth3_tx_data0>,
90				<&iomuxc_gpio_emc_b1_06_eth3_tx_data1>,
91				<&iomuxc_gpio_emc_b1_07_eth3_tx_en>,
92				<&iomuxc_gpio_emc_b1_08_eth3_tx_clk>,
93				<&iomuxc_gpio_emc_b1_09_eth3_rx_data0>,
94				<&iomuxc_gpio_emc_b1_10_eth3_rx_data1>,
95				<&iomuxc_gpio_emc_b1_11_eth3_rx_en>;
96			bias-pull-down;
97			slew-rate = "fast";
98			drive-strength = "high";
99		};
100	};
101
102	eth4_default: eth4_default {
103		group1 {
104			pinmux = <&iomuxc_gpio_emc_b2_13_eth4_tx_data0>,
105				<&iomuxc_gpio_emc_b2_14_eth4_tx_data1>,
106				<&iomuxc_gpio_emc_b2_15_eth4_tx_en>,
107				<&iomuxc_gpio_emc_b2_17_eth4_rx_data0>,
108				<&iomuxc_gpio_emc_b2_18_eth4_rx_data1>,
109				<&iomuxc_gpio_emc_b2_19_eth4_rx_en>,
110				<&iomuxc_gpio_emc_b2_20_eth4_rx_er>;
111			bias-pull-down;
112			slew-rate = "fast";
113			drive-strength = "high";
114		};
115		group2 {
116			pinmux = <&iomuxc_gpio_emc_b2_16_eth4_tx_clk>;
117			input-enable;
118			bias-pull-down;
119			slew-rate = "fast";
120			drive-strength = "high";
121		};
122	};
123
124	pinmux_lpspi3: pinmux_lpspi3 {
125		group0 {
126			pinmux = <&iomuxc_gpio_sd_b1_00_lpspi3_pcs0>,
127				<&iomuxc_gpio_sd_b1_01_lpspi3_sck>,
128				<&iomuxc_gpio_sd_b1_02_lpspi3_sout>,
129				<&iomuxc_gpio_sd_b1_03_lpspi3_sin>;
130			drive-strength = "high";
131			slew-rate = "fast";
132		};
133	};
134
135	pinmux_lpuart1: pinmux_lpuart1 {
136		group0 {
137			pinmux = <&iomuxc_aon_gpio_aon_09_lpuart1_rxd>,
138				<&iomuxc_aon_gpio_aon_08_lpuart1_txd>;
139			drive-strength = "high";
140			slew-rate = "fast";
141		};
142	};
143
144	pinmux_lpuart1_sleep: pinmux_lpuart1_sleep {
145		group0 {
146			pinmux = <&iomuxc_aon_gpio_aon_09_gpio1_io09>;
147			drive-strength = "high";
148			bias-pull-up;
149			slew-rate = "fast";
150		};
151		group1 {
152			pinmux = <&iomuxc_aon_gpio_aon_08_lpuart1_txd>;
153			drive-strength = "high";
154			slew-rate = "fast";
155		};
156	};
157
158	pinmux_lpuart12: pinmux_lpuart12 {
159		group0 {
160			pinmux = <&iomuxc_aon_gpio_aon_20_lpuart12_rxd>,
161				<&iomuxc_aon_gpio_aon_19_lpuart12_txd>;
162			drive-strength = "high";
163			slew-rate = "fast";
164		};
165	};
166
167	pinmux_lpuart12_sleep: pinmux_lpuart12_sleep {
168		group0 {
169			pinmux = <&iomuxc_aon_gpio_aon_20_lpuart12_rxd>;
170			drive-strength = "high";
171			bias-pull-up;
172			slew-rate = "fast";
173		};
174		group1 {
175			pinmux = <&iomuxc_aon_gpio_aon_19_lpuart12_txd>;
176			drive-strength = "high";
177			slew-rate = "fast";
178		};
179	};
180
181	pinmux_lpuart3: pinmux_lpuart3 {
182		group0 {
183			pinmux = <&iomuxc_gpio_ad_14_lpuart3_rxd>,
184				<&iomuxc_gpio_ad_13_lpuart3_txd>;
185			drive-strength = "high";
186			slew-rate = "fast";
187		};
188	};
189
190	pinmux_lpuart3_sleep: pinmux_lpuart3_sleep {
191		group0 {
192			pinmux = <&iomuxc_gpio_ad_14_gpio4_io14>;
193			drive-strength = "high";
194			bias-pull-up;
195			slew-rate = "fast";
196		};
197		group1 {
198			pinmux = <&iomuxc_gpio_ad_13_lpuart3_txd>;
199			drive-strength = "high";
200			slew-rate = "fast";
201		};
202	};
203
204	/* Connected to FXLS8974 */
205	pinmux_lpi2c2: pinmux_lpi2c2 {
206		group0 {
207			pinmux = <&iomuxc_aon_gpio_aon_15_lpi2c2_sda>,
208				<&iomuxc_aon_gpio_aon_16_lpi2c2_scl>;
209			drive-strength = "normal";
210			drive-open-drain;
211			slew-rate = "fast";
212			input-enable;
213		};
214	};
215
216	pinmux_lpi2c3: pinmux_lpi2c3 {
217		group0 {
218			pinmux = <&iomuxc_gpio_ad_18_lpi2c3_scl>,
219				<&iomuxc_gpio_ad_19_lpi2c3_sda>;
220			drive-strength = "normal";
221			drive-open-drain;
222			slew-rate = "fast";
223			input-enable;
224		};
225	};
226
227	pinmux_lpadc1: pinmux_lpadc1 {
228		group0 {
229			pinmux = <&iomuxc_gpio_ad_16_adc1_ch0a>,
230				<&iomuxc_gpio_ad_14_adc1_ch1a>;
231			drive-strength = "high";
232			bias-pull-down;
233			slew-rate = "fast";
234		};
235	};
236
237	/* Need to weld pin header on J35 */
238	pinmux_flexcan3: pinmux_flexcan3 {
239		group0 {
240			pinmux = <&iomuxc_aon_gpio_aon_03_flexcan3_rx>,
241				<&iomuxc_aon_gpio_aon_18_flexcan3_tx>;
242			drive-strength = "high";
243			slew-rate = "fast";
244		};
245	};
246
247	pinmux_flexspi1: pinmux_flexspi1 {
248		group0 {
249			pinmux = <&iomuxc_gpio_sd_b2_05_flexspi1_b_dqs>,
250				<&iomuxc_gpio_sd_b2_06_flexspi1_b_ss0_b>,
251				<&iomuxc_gpio_sd_b2_07_flexspi1_b_sclk>,
252				<&iomuxc_gpio_sd_b2_08_flexspi1_b_data0>,
253				<&iomuxc_gpio_sd_b2_09_flexspi1_b_data1>,
254				<&iomuxc_gpio_sd_b2_10_flexspi1_b_data2>,
255				<&iomuxc_gpio_sd_b2_11_flexspi1_b_data3>;
256			bias-pull-down;
257			input-enable;
258		};
259	};
260
261	pinmux_flexpwm2: pinmux_flexpwm2 {
262		group0 {
263			pinmux = <&iomuxc_gpio_ad_27_flexpwm2_pwm1_b>;
264			drive-strength = "high";
265			slew-rate = "fast";
266		};
267	};
268
269	pinmux_tpm5: pinmux_tpm5 {
270		group0 {
271			pinmux = <&iomuxc_gpio_b1_00_tpm5_ch0>;
272			drive-strength = "normal";
273			slew-rate = "slow";
274		};
275	};
276
277	pinmux_i3c2: pinmux_i3c2 {
278		group0 {
279			pinmux = <&iomuxc_gpio_ad_18_i3c2_scl>,
280				<&iomuxc_gpio_ad_19_i3c2_sda>;
281			drive-strength = "normal";
282			drive-open-drain;
283			slew-rate = "fast";
284			input-enable;
285		};
286
287		group1 {
288			pinmux = <&iomuxc_gpio_ad_17_i3c2_pur>;
289			slew-rate = "fast";
290			drive-strength = "high";
291		};
292	};
293
294	pinmux_usdhc1: pinmux_usdhc1 {
295		group0 {
296			pinmux = <&iomuxc_gpio_sd_b1_00_usdhc1_cmd>,
297				<&iomuxc_gpio_sd_b1_01_usdhc1_clk>,
298				<&iomuxc_gpio_sd_b1_02_usdhc1_data0>,
299				<&iomuxc_gpio_sd_b1_03_usdhc1_data1>,
300				<&iomuxc_gpio_sd_b1_04_usdhc1_data2>,
301				<&iomuxc_gpio_sd_b1_05_usdhc1_data3>;
302			bias-pull-up;
303			input-enable;
304		};
305		group1 {
306			pinmux = <&iomuxc_gpio_ad_34_usdhc1_vselect>,
307				<&iomuxc_gpio_ad_15_gpio4_io15>;
308			drive-strength = "high";
309			bias-pull-down;
310			slew-rate = "fast";
311		};
312		group2 {
313			pinmux = <&iomuxc_gpio_ad_14_gpio4_io14>;
314			drive-strength = "high";
315			bias-pull-up;
316			slew-rate = "fast";
317		};
318	};
319
320	/* removes pull on dat3 for card detect */
321	pinmux_usdhc1_dat3_nopull: pinmux_usdhc1_dat3_nopull {
322		group0 {
323			pinmux = <&iomuxc_gpio_sd_b1_05_usdhc1_data3>;
324			bias-disable;
325			input-enable;
326		};
327		group1 {
328			pinmux = <&iomuxc_gpio_sd_b1_00_usdhc1_cmd>,
329				<&iomuxc_gpio_sd_b1_01_usdhc1_clk>,
330				<&iomuxc_gpio_sd_b1_02_usdhc1_data0>,
331				<&iomuxc_gpio_sd_b1_03_usdhc1_data1>,
332				<&iomuxc_gpio_sd_b1_04_usdhc1_data2>;
333			bias-pull-up;
334			input-enable;
335		};
336		group2 {
337			pinmux = <&iomuxc_gpio_ad_34_usdhc1_vselect>,
338				<&iomuxc_gpio_ad_15_gpio4_io15>;
339			drive-strength = "high";
340			bias-pull-down;
341			slew-rate = "fast";
342		};
343		group3 {
344			pinmux = <&iomuxc_gpio_ad_14_gpio4_io14>;
345			drive-strength = "high";
346			bias-pull-up;
347			slew-rate = "fast";
348		};
349	};
350};
351