1# Copyright 2023 The ChromiumOS Authors
2# SPDX-License-Identifier: Apache-2.0
3
4orsource "*/Kconfig.defconfig"
5
6if SOC_FAMILY_MTK
7
8config INTC_MTK_ADSP
9	default y
10
11config XTENSA_SMALL_VECTOR_TABLE_ENTRY
12	default y
13
14config XTENSA_USE_CORE_CRT1
15	default n
16
17config MULTI_LEVEL_INTERRUPTS
18	default y
19config 2ND_LEVEL_INTERRUPTS
20	default y
21config MAX_IRQ_PER_AGGREGATOR
22	default 32
23config 2ND_LVL_ISR_TBL_OFFSET
24	default 32
25
26# The 8186/8188 core has only one software interrupt that lives at
27# level 2, underneath other hardware interrupts like timer, so it
28# can't reliably do this.  Unselect so the tests don't try to exercise
29# it.
30config IRQ_OFFLOAD_NESTED
31	default n if SOC_SERIES_MT818X
32	default y
33
34config CPU_HAS_DCACHE
35	default y
36config DCACHE
37	default y
38config CACHE_MANAGEMENT
39	default y
40config DCACHE_LINE_SIZE
41	default 128
42
43config NOCACHE_MEMORY
44	default y
45
46config MTK_ADSP_TIMER
47	default y
48config XTENSA_TIMER
49	default n
50
51config CONSOLE
52	default y
53config WINSTREAM_CONSOLE
54	default y
55config WINSTREAM
56	default y
57config LOG_BACKEND_ADSP
58	default y if LOG
59
60config XTENSA_CCOUNT_HZ
61	default 720000000 if SOC_MT8195
62	default 400000000 if SOC_MT8186
63	default 800000000 if SOC_MT8188
64	default 800000000 if SOC_MT8196
65
66config SYS_CLOCK_HW_CYCLES_PER_SEC
67	default $(dt_node_int_prop_int,$(dt_nodelabel_path,ostimer64),freq-hz)
68
69config MAIN_STACK_SIZE
70	default 2048
71
72# This platform has a single big DRAM region where most linkage
73# happens.  The libc heap normally wants to steal all of it, when in
74# fact SOF has its own heap.  Just leave a little for stray malloc()
75# calls to find.
76config COMMON_LIBC_MALLOC_ARENA_SIZE
77	default 32768
78
79# Don't build the HAL if the toolchain already includes it.  Note that
80# this is done in the SOC layer historically, really this belongs in
81# arch/xtensa or the toolchain integration.
82#
83config XTENSA_HAL
84	default n if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xcc"
85	default n if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xt-clang"
86	default y
87
88config SOC_TOOLCHAIN_NAME
89	default "mtk_mt8195_adsp" if SOC_SERIES_MT8195
90	default "mtk_mt818x_adsp" if SOC_SERIES_MT818X
91	default "mtk_mt8196_adsp" if SOC_SERIES_MT8196
92
93config XTENSA_RESET_VECTOR
94	default n
95
96# This single-core device doesn't have S32C1I and so has no built-in
97# atomics.  Note we must disable _ARCH explicitly because
98# CONFIG_XTENSA turns it on (due to an xcc lack of gcc builtins?)
99#
100config ATOMIC_OPERATIONS_C
101	default y
102config ATOMIC_OPERATIONS_ARCH
103	default n
104
105config GEN_ISR_TABLES
106	default y
107config GEN_SW_ISR_TABLE
108	default y
109config GEN_IRQ_VECTOR_TABLE
110	default n
111
112endif # SOC_FAMILY_MTK
113