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/Zephyr-latest/doc/hardware/peripherals/
Dpeci.rst11 The PECI interface allows external devices to read processor temperature,
12 perform processor manageability functions, and manage processor interface
/Zephyr-latest/boards/intel/niosv_g/doc/
Dindex.rst23 For example, Arria10 Nios® V/g processor example design system prebuilt files can be downloaded fro…
24 …t/www/us/en/design-example/776196/intel-arria-10-fpga-hello-world-design-on-nios-v-g-processor.html
28 Create Nios® V/g processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/g processor based system into the FPGA …
33 In order to create the Nios® V/g processor inside the FPGA device, please download the generated .s…
44 top.sof is referring to Nios® V/m processor based system SRAM Object File.
55 Use the JTAG UART terminal to print the stdout and stderr of the Nios® V/g processor system.
/Zephyr-latest/drivers/pinctrl/
DKconfig.xlnx5 bool "Xilinx Zynq 7000 processor system MIO pin controller driver"
10 Enable the Xilinx Zynq 7000 processor system MIO pin controller driver.
/Zephyr-latest/boards/intel/niosv_m/doc/
Dindex.rst23 For example, Arria10 Nios® V/m processor example design system prebuilt files can be downloaded fro…
28 Create Nios® V/m processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/m processor based system into the FPGA …
33 In order to create the Nios® V/m processor inside the FPGA device, please download the generated .s…
44 top.sof is referring to Nios® V/m processor based system SRAM Object File.
55 Use the JTAG UART terminal to print the stdout and stderr of the Nios® V/m processor system.
/Zephyr-latest/modules/thrift/src/thrift/server/
DTServer.h177 TServer(const std::shared_ptr<TProcessor> &processor) in TServer() argument
178 : processorFactory_(new TSingletonProcessorFactory(processor)) in TServer()
204 TServer(const std::shared_ptr<TProcessor> &processor, in TServer() argument
206 : processorFactory_(new TSingletonProcessorFactory(processor)), in TServer()
230 TServer(const std::shared_ptr<TProcessor> &processor, in TServer() argument
234 : processorFactory_(new TSingletonProcessorFactory(processor)), in TServer()
255 TServer(const std::shared_ptr<TProcessor> &processor, in TServer() argument
261 : processorFactory_(new TSingletonProcessorFactory(processor)), in TServer()
DTServerFramework.cpp58 TServerFramework::TServerFramework(const shared_ptr<TProcessor> &processor, in TServerFramework() argument
62 : TServer(processor, serverTransport, transportFactory, protocolFactory), clients_(0), in TServerFramework()
79 TServerFramework::TServerFramework(const shared_ptr<TProcessor> &processor, in TServerFramework() argument
85 : TServer(processor, serverTransport, inputTransportFactory, outputTransportFactory, in TServerFramework()
/Zephyr-latest/boards/renesas/rcar_salvator_x/support/
Dopenocd.cfg39 # This function make use of A5x processor to:
42 # - Halt the processor
63 # resume a5x processor or cmt timer will not run
65 # set CR7 processor as default target for future commands
72 # Resume the A57 processor and gives
/Zephyr-latest/boards/intel/adl/doc/
Dindex.rst8 Alder Lake processor is a 64-bit multi-core processor built on 10-nanometer
11 Currently supported is N-processor line, Single Chip Platform that consists of
65 .. _INTEL_ADL: https://edc.intel.com/content/www/us/en/design/products/platforms/processor-and-core…
/Zephyr-latest/boards/microchip/mec172xevb_assy6906/
DKconfig.defconfig27 # processor clock divider register. We assume PCR processor clock divider
/Zephyr-latest/boards/microchip/mec172xmodular_assy6930/
DKconfig.defconfig27 # processor clock divider register. We assume PCR processor clock divider
/Zephyr-latest/samples/modules/thrift/hello/server/src/
Dmain.cpp75 std::shared_ptr<TProcessor> processor(new HelloProcessor(handler)); in main() local
117 TSimpleServer server(processor, serverTransport, transportFactory, protocolFactory); in main()
/Zephyr-latest/doc/hardware/cache/
Dguide.rst27 When dealing with memory shared between a processor core and other bus masters,
28 cache coherency needs to be considered. Typically processor caches exist as
29 close to each processor core as possible to maximize performance gain. Because
31 processor's cache, resulting in what appears to be corrupt data. If you are
32 moving data using DMA and the processor doesn't see the data you expect, cache
35 There are multiple approaches to ensuring that the data seen by the processor
140 processor has written to it and before a remote bus master reads from that
146 caching in which data writes from the processor core propagate through to
153 be refreshed from main memory when the processor next reads from the specified
160 the processor reads from the buffer.
/Zephyr-latest/tests/modules/thrift/ThriftTest/src/
Dmain.cpp90 std::shared_ptr<TProcessor> processor(new ThriftTestProcessor(handler)); in setup_server() local
112 TSimpleServer server(processor, serverTransport, transportFactory, protocolFactory); in setup_server()
114 new TSimpleServer(processor, serverTransport, transportFactory, protocolFactory)); in setup_server()
/Zephyr-latest/samples/subsys/ipc/openamp/boards/
Dlpcxpresso54114_lpc54114_m4.overlay10 * shared memory reserved for the inter-processor communication
Dv2m_musca_b1.overlay10 * shared memory reserved for the inter-processor communication
Dmps2_an521_cpu0.overlay10 * shared memory reserved for the inter-processor communication
/Zephyr-latest/samples/subsys/ipc/openamp/remote/boards/
Dlpcxpresso54114_lpc54114_m0.overlay10 * shared memory reserved for the inter-processor communication
Dv2m_musca_b1_musca_b1_ns.overlay10 * shared memory reserved for the inter-processor communication
Dmps2_an521_cpu1.overlay10 * shared memory reserved for the inter-processor communication
/Zephyr-latest/samples/subsys/ipc/rpmsg_service/boards/
Dv2m_musca_b1.overlay10 * shared memory reserved for the inter-processor communication
Dmps2_an521_cpu0.overlay10 * shared memory reserved for the inter-processor communication
/Zephyr-latest/samples/subsys/ipc/openamp_rsc_table/boards/
Dimx8mp_evk_mimx8ml8_m7.overlay10 * shared memory reserved for the inter-processor communication
/Zephyr-latest/samples/subsys/ipc/rpmsg_service/remote/boards/
Dv2m_musca_b1_musca_b1_ns.overlay10 * shared memory reserved for the inter-processor communication
Dmps2_an521_cpu1.overlay10 * shared memory reserved for the inter-processor communication
/Zephyr-latest/samples/subsys/ipc/openamp_rsc_table/snippets/
Dnxp-openamp-imx8-adsp.overlay10 * shared memory reserved for the inter-processor communication

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