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Searched refs:mstatus (Results 1 – 22 of 22) sorted by relevance

/Zephyr-latest/arch/riscv/core/
Dfpu.c65 unsigned long status = csr_read(mstatus); in z_riscv_fpu_disable()
70 csr_clear(mstatus, MSTATUS_FS); in z_riscv_fpu_disable()
79 __ASSERT((csr_read(mstatus) & MSTATUS_IEN) == 0, in z_riscv_fpu_load()
81 __ASSERT((csr_read(mstatus) & MSTATUS_FS) == 0, in z_riscv_fpu_load()
88 csr_set(mstatus, MSTATUS_FS_INIT); in z_riscv_fpu_load()
103 __ASSERT((csr_read(mstatus) & MSTATUS_IEN) == 0, in arch_flush_local_fpu()
105 __ASSERT((csr_read(mstatus) & MSTATUS_FS) == 0, in arch_flush_local_fpu()
115 csr_set(mstatus, MSTATUS_FS_CLEAN); in arch_flush_local_fpu()
124 csr_clear(mstatus, MSTATUS_FS); in arch_flush_local_fpu()
135 __ASSERT((csr_read(mstatus) & MSTATUS_IEN) == 0, in flush_owned_fpu()
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Dthread.c66 stack_init->mstatus = MSTATUS_DEF_RESTORE; in arch_new_thread()
73 stack_init->mstatus |= MSTATUS_FS_INIT; in arch_new_thread()
96 stack_init->mstatus |= MSTATUS_MPRV; in arch_new_thread()
159 status = csr_read(mstatus); in arch_user_mode_enter()
168 csr_write(mstatus, status); in arch_user_mode_enter()
Disr.S148 csrr t0, mstatus
206 csrr t2, mstatus
366 csrr t0, mstatus
405 csrc mstatus, t1
407 csrs mstatus, t1
523 csrs mstatus, MSTATUS_IEN
577 csrc mstatus, MSTATUS_IEN
599 csrc mstatus, t1
601 csrs mstatus, t1
741 csrw mstatus, t2
Dfatal.c43 if ((esf->mstatus & MSTATUS_MPP) == PRV_U) { in z_riscv_get_sp_before_exc()
123 LOG_ERR("mstatus: " PR_REG, esf->mstatus); in z_riscv_fatal_error_csf()
193 if ((esf->mstatus & MSTATUS_MPP) == 0 && in bad_stack_pointer()
Dpmp.c396 csr_set(mstatus, MSTATUS_MPRV); in z_riscv_pmp_init()
515 csr_clear(mstatus, MSTATUS_MPRV | MSTATUS_MPP); in z_riscv_pmp_stackguard_enable()
527 csr_set(mstatus, MSTATUS_MPRV); in z_riscv_pmp_stackguard_enable()
546 csr_clear(mstatus, MSTATUS_MPRV); in z_riscv_pmp_stackguard_disable()
668 csr_clear(mstatus, MSTATUS_MPRV); in z_riscv_pmp_usermode_enable()
Dipi_clint.c61 csr_clear(mstatus, MSTATUS_IEN); in sched_ipi_handler()
Dreset.S53 csrs mstatus, t0
/Zephyr-latest/tests/arch/riscv/fpu_sharing/src/
Dmain.c16 return csr_read(mstatus) & MSTATUS_FS; in fpu_state()
273 csr_set(mstatus, MSTATUS_IEN); in exception_context()
285 zassert_true((csr_read(mstatus) & MSTATUS_IEN) == 0, "IRQs should be disabled"); in exception_context()
297 zassert_true((csr_read(mstatus) & MSTATUS_IEN) != 0, "IRQs should be enabled"); in ZTEST()
301 zassert_true((csr_read(mstatus) & MSTATUS_IEN) != 0, "IRQs should be enabled"); in ZTEST()
314 zassert_true((csr_read(mstatus) & MSTATUS_IEN) != 0, "IRQs should be enabled"); in ZTEST()
325 zassert_true((csr_read(mstatus) & MSTATUS_IEN) != 0, "IRQs should be enabled"); in ZTEST()
/Zephyr-latest/soc/openisa/rv32m1/
Dwdog.S42 csrrc t0, mstatus, MSTATUS_IEN
62 csrrs x0, mstatus, t0
/Zephyr-latest/soc/nordic/common/vpr/
Dsoc_isr_stacking.h22 unsigned long mstatus; \
45 unsigned long mstatus; \
/Zephyr-latest/soc/espressif/esp32c6/
Dsoc.c45 csr_read_clear(mstatus, MSTATUS_MIE); in __esp_platform_start()
/Zephyr-latest/soc/gd/gd32/gd32vf103/
Dentry.S15 csrc mstatus, MSTATUS_MIE
/Zephyr-latest/soc/espressif/esp32c2/
Dsoc.c49 csr_read_clear(mstatus, MSTATUS_MIE); in __esp_platform_start()
/Zephyr-latest/soc/espressif/esp32c3/
Dsoc.c49 csr_read_clear(mstatus, MSTATUS_MIE); in __esp_platform_start()
/Zephyr-latest/include/zephyr/arch/riscv/
Dexception.h82 unsigned long mstatus; /* machine status register */ member
/Zephyr-latest/soc/neorv32/
Dreset.S20 csrw mstatus, x0
/Zephyr-latest/drivers/cache/
Dcache_andes.c83 unsigned long status = csr_read(mstatus); in nds_cctl_range_operations()
112 unsigned long status = csr_read(mstatus); in nds_l1i_cache_all()
140 unsigned long status = csr_read(mstatus); in nds_l1d_cache_all()
231 unsigned long status = csr_read(mstatus); in cache_data_disable()
Dcache_andes_l2.h84 unsigned long status = csr_read(mstatus); in nds_l2_cache_all()
/Zephyr-latest/drivers/i3c/
Di3c_mcux.c238 uint32_t mstatus, merrwarn; in mcux_i3c_has_error() local
240 mstatus = base->MSTATUS; in mcux_i3c_has_error()
241 if ((mstatus & I3C_MSTATUS_ERRWARN_MASK) == I3C_MSTATUS_ERRWARN_MASK) { in mcux_i3c_has_error()
251 mstatus, merrwarn); in mcux_i3c_has_error()
515 uint32_t mstatus = base->MSTATUS; in mcux_i3c_state_get() local
519 state = (mstatus & I3C_MSTATUS_STATE_MASK) >> I3C_MSTATUS_STATE_SHIFT; in mcux_i3c_state_get()
1464 uint32_t mstatus, ibitype, ibiaddr; in mcux_i3c_ibi_work() local
1481 mstatus = sys_read32((mem_addr_t)&base->MSTATUS); in mcux_i3c_ibi_work()
1482 ibiaddr = (mstatus & I3C_MSTATUS_IBIADDR_MASK) >> I3C_MSTATUS_IBIADDR_SHIFT; in mcux_i3c_ibi_work()
1488 ibitype = (mstatus & I3C_MSTATUS_IBITYPE_MASK); in mcux_i3c_ibi_work()
/Zephyr-latest/soc/sensry/ganymed/sy1xx/common/
Dcrt0.S24 csrwi mstatus, 0x00
/Zephyr-latest/arch/riscv/core/offsets/
Doffsets.c113 GEN_OFFSET_STRUCT(arch_esf, mstatus);
/Zephyr-latest/arch/riscv/
DKconfig144 writing the mstatus register to lock and unlock the IRQs.