1/* Copyright 2023 The ChromiumOS Authors
2 * SPDX-License-Identifier: Apache-2.0
3 */
4#include <mem.h>
5
6/dts-v1/;
7/ {
8
9	#address-cells = <1>;
10	#size-cells = <1>;
11
12	sram0: memory@40000000 {
13		 device_type = "memory";
14		 compatible = "mmio-sram";
15		 reg = <0x40000000 DT_SIZE_K(256)>;
16	};
17
18	dram0: memory@60000000 {
19		device_type = "memory";
20		compatible = "mmio-sram";
21		reg = <0x60000000 DT_SIZE_K(13824)>;
22	};
23
24	dram1: memory@60e80000 {
25		device_type = "memory";
26		compatible = "mmio-sram";
27		reg = <0x60e80000 DT_SIZE_K(2560)>;
28	};
29
30	soc {
31		#address-cells = <1>;
32		#size-cells = <1>;
33
34		cpuclk: cpuclk@10000000 {
35			compatible = "mediatek,mt8195_cpuclk";
36			reg = <0x10000000 380>;
37			cg-reg = <0x10720180>;
38			pll-ctrl-reg = <0x1000c7e0>;
39			freqs-mhz = <26 370 540 720>;
40		};
41
42		core_intc: core_intc@0 {
43			compatible = "cdns,xtensa-core-intc";
44			reg = <0 4>;
45			interrupt-controller;
46			#interrupt-cells = <3>;
47		};
48
49		intc1: intc@10680130 {
50			compatible = "mediatek,adsp_intc";
51			interrupt-controller;
52			#interrupt-cells = <3>;
53			reg = <0x10680130 4>;
54			status-reg = <0x10680150>;
55			interrupts = <1 0 0>;
56			mask = <0x3ffffff0>;
57			interrupt-parent = <&core_intc>;
58		};
59
60		intc23: intc@108030f4 {
61			compatible = "mediatek,adsp_intc";
62			interrupt-controller;
63			#interrupt-cells = <3>;
64			reg = <0x108030f4 4>;
65			status-reg = <0x108030fc>;
66			interrupts = <23 0 0>;
67			mask = <0xffff>;
68			interrupt-parent = <&core_intc>;
69		};
70
71		ostimer64: ostimer64@1080d080 {
72			compatible = "mediatek,ostimer64";
73			reg = <0x1080d080 28>;
74		};
75
76		ostimer0: ostimer@1080d000 {
77			compatible = "mediatek,ostimer";
78			reg = <0x1080d000 16>;
79			interrupt-parent = <&intc23>;
80			interrupts = <11 0 0>;
81		};
82
83		mbox0: mbox@10816000 {
84			compatible = "mediatek,mbox";
85			reg = <0x10816000 56>;
86			interrupt-parent = <&intc23>;
87			interrupts = <0 0 0>;
88		};
89
90		mbox1: mbox@10817000 {
91			compatible = "mediatek,mbox";
92			reg = <0x10817000 56>;
93			interrupt-parent = <&intc23>;
94			interrupts = <1 0 0>;
95		};
96	}; /* soc */
97
98	chosen { };
99	aliases { };
100};
101