Searched refs:get_port (Results 1 – 3 of 3) sorted by relevance
120 static inline uint32_t get_port(const struct gpio_efinix_sapphire_cfg *config) in get_port() function136 *value = get_port(config); in gpio_efinix_sapphire_port_get_raw()145 uint32_t c_reg_val = get_port(config); in gpio_efinix_sapphire_port_set_masked_raw()160 uint32_t c_reg_val = get_port(config); in gpio_efinix_sapphire_port_set_bits_raw()174 uint32_t c_reg_val = get_port(config); in gpio_efinix_sapphire_port_clear_bits_raw()188 uint32_t c_reg_val = get_port(config); in gpio_efinix_sapphire_port_toggle_bits()
84 static inline uint32_t get_port(const struct gpio_litex_cfg *config) in get_port() function136 *value = get_port(gpio_config); in gpio_litex_port_get_raw()147 port_val = get_port(gpio_config); in gpio_litex_port_set_masked_raw()160 port_val = get_port(gpio_config); in gpio_litex_port_set_bits_raw()173 port_val = get_port(gpio_config); in gpio_litex_port_clear_bits_raw()186 port_val = get_port(gpio_config); in gpio_litex_port_toggle_bits()
247 #define THR(dev) (get_port(dev) + (REG_THR * reg_interval(dev)))248 #define RDR(dev) (get_port(dev) + (REG_RDR * reg_interval(dev)))249 #define BRDL(dev) (get_port(dev) + (REG_BRDL * reg_interval(dev)))250 #define BRDH(dev) (get_port(dev) + (REG_BRDH * reg_interval(dev)))251 #define IER(dev) (get_port(dev) + (REG_IER * reg_interval(dev)))252 #define IIR(dev) (get_port(dev) + (REG_IIR * reg_interval(dev)))253 #define FCR(dev) (get_port(dev) + (REG_FCR * reg_interval(dev)))254 #define LCR(dev) (get_port(dev) + (REG_LCR * reg_interval(dev)))255 #define MDC(dev) (get_port(dev) + (REG_MDC * reg_interval(dev)))256 #define LSR(dev) (get_port(dev) + (REG_LSR * reg_interval(dev)))[all …]
