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/Zephyr-latest/subsys/bindesc/
Dbindesc_build_time.h.in4 #define _BINDESC_BUILD_TIME_H_
6 #define BUILD_TIME_YEAR @BUILD_TIME_YEAR@
7 #define BUILD_TIME_MONTH @BUILD_TIME_MONTH@
8 #define BUILD_TIME_DAY @BUILD_TIME_DAY@
9 #define BUILD_TIME_HOUR @BUILD_TIME_HOUR@
10 #define BUILD_TIME_MINUTE @BUILD_TIME_MINUTE@
11 #define BUILD_TIME_SECOND @BUILD_TIME_SECOND@
12 #define BUILD_TIME_UNIX @BUILD_TIME_UNIX@
14 #define BUILD_DATE_TIME_STRING "@BUILD_DATE_TIME_STRING@"
15 #define BUILD_DATE_STRING "@BUILD_DATE_STRING@"
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/Zephyr-latest/
Dversion.h.in2 #define _@VERSION_TYPE@_VERSION_H_
12 #define @VERSION_TYPE@VERSION @@VERSION_TYPE@VERSION@
13 #define @VERSION_TYPE@_VERSION_NUMBER @@VERSION_TYPE@_VERSION_NUMBER@
14 #define @VERSION_TYPE@_VERSION_MAJOR @@VERSION_TYPE@_VERSION_MAJOR@
15 #define @VERSION_TYPE@_VERSION_MINOR @@VERSION_TYPE@_VERSION_MINOR@
16 #define @VERSION_TYPE@_PATCHLEVEL @@VERSION_TYPE@_PATCHLEVEL@
17 #define @VERSION_TYPE@_TWEAK @@VERSION_TYPE@_VERSION_TWEAK@
18 #define @VERSION_TYPE@_VERSION_STRING "@@VERSION_TYPE@_VERSION_STRING@"
19 #define @VERSION_TYPE@_VERSION_EXTENDED_STRING "@@VERSION_TYPE@_VERSION_EXTENDED_STRING@"
20 #define @VERSION_TYPE@_VERSION_TWEAK_STRING "@@VERSION_TYPE@_VERSION_TWEAK_STRING@"
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/Zephyr-latest/samples/application_development/code_relocation_nocopy/
Dlinker_arm_nocopy.ld24 #define EXTFLASH_NODE DT_INST(0, nordic_qspi_nor)
25 #define EXTFLASH_ADDR 0x10000000
26 #define EXTFLASH_SIZE DT_PROP_OR(EXTFLASH_NODE, size_in_bytes, \
32 #define EXTFLASH_NODE DT_INST(0, st_stm32_ospi_nor)
33 #define EXTFLASH_ADDR DT_REG_ADDR(DT_INST(0, st_stm32_ospi_nor))
34 #define EXTFLASH_SIZE DT_REG_ADDR_BY_IDX(DT_INST(0, st_stm32_ospi_nor), 1)
39 #define EXTFLASH_NODE DT_INST(0, st_stm32_qspi_nor)
40 #define EXTFLASH_ADDR DT_REG_ADDR(DT_INST(0, st_stm32_qspi_nor))
41 #define EXTFLASH_SIZE DT_REG_ADDR_BY_IDX(DT_INST(0, st_stm32_qspi_nor), 1)
46 #define EXTFLASH_NODE DT_INST(0, st_stm32_xspi_nor)
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/Zephyr-latest/dts/arm/ti/
Dcc32xx.dtsi9 #define INT_UARTA0 21 // UART0 Rx and Tx
10 #define INT_UARTA1 22 // UART1 Rx and Tx
11 #define INT_I2CA0 24 // I2C controller
12 #define INT_ADCCH0 30 // ADC channel 0
13 #define INT_ADCCH1 31 // ADC channel 1
14 #define INT_ADCCH2 32 // ADC channel 2
15 #define INT_ADCCH3 33 // ADC channel 3
16 #define INT_WDT 34 // Watchdog Timer
20 #define EXP_UARTA0 (INT_UARTA0 - 16)
21 #define EXP_UARTA1 (INT_UARTA1 - 16)
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/Zephyr-latest/soc/snps/arc_iot/
Dlinker.ld19 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
20 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
25 #define FLASH_START DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
26 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
32 #define ICCM_START DT_REG_ADDR(DT_INST(0, arc_iccm))
33 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
41 #define DCCM_START DT_REG_ADDR(DT_INST(0, arc_dccm))
42 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-latest/arch/arm/core/cortex_m/tz/
Dsecure_entry_functions.ld10 #define __NSC_ALIGN (ALIGN(CONFIG_NRF_SPU_FLASH_REGION_SIZE) \
12 #define NSC_ALIGN \
15 #define NSC_ALIGN_END . = ALIGN(CONFIG_NRF_SPU_FLASH_REGION_SIZE)
20 #define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)
23 #define NSC_ALIGN . = ALIGN(32)
28 #define NSC_ALIGN_END . = ALIGN(32)
45 #define NRF_SG_START (__sg_start % CONFIG_NRF_SPU_FLASH_REGION_SIZE)
46 #define NRF_SG_SIZE (CONFIG_NRF_SPU_FLASH_REGION_SIZE - NRF_SG_START)
/Zephyr-latest/soc/snps/nsim/arc_classic/
Dlinker.ld16 #define ICCM_START DT_REG_ADDR(DT_INST(0, arc_iccm))
17 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
26 #define DCCM_START DT_REG_ADDR(DT_INST(0, arc_dccm))
27 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
32 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
33 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
39 #define FLASH_START DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
40 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-latest/tests/application_development/code_relocation/
Dlinker_arm_sram2.ld24 #define CONFIG_SRAM2 1
25 #define _SRAM2_DATA_SECTION_NAME .sram2_data
26 #define _SRAM2_BSS_SECTION_NAME .sram2_bss
27 #define _SRAM2_TEXT_SECTION_NAME .sram2_text
28 #define SRAM2_ADDR (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2)
31 #define RAM_SIZE2 (CONFIG_SRAM_SIZE * 512)
Dlinker_riscv_qemu_sram2.ld16 #define _SRAM2_DATA_SECTION_NAME .sram2_data
17 #define _SRAM2_BSS_SECTION_NAME .sram2_bss
18 #define _SRAM2_TEXT_SECTION_NAME .sram2_text
19 #define SRAM2_ADDR (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2)
21 #define RAM_SIZE2 (CONFIG_SRAM_SIZE * 512)
Dlinker_xtensa_qemu_sram2.ld13 #define SRAM2_ADDR (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2)
14 #define RAM_SIZE2 (0x4000000)
26 #define MPU_ALIGN(region_size) \
/Zephyr-latest/include/zephyr/arch/arc/v2/
Dxy_mem.ld9 #define XCCM_START DT_REG_ADDR(DT_INST(0, arc_xccm))
10 #define XCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_xccm))
15 #define YCCM_START DT_REG_ADDR(DT_INST(0, arc_yccm))
16 #define YCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_yccm))
/Zephyr-latest/samples/boards/arc_secure_services/
Dnsim_sem_normal.dts12 #define ICCM_ADDR 40000
13 #define ICCM_SIZE DT_SIZE_K(256)
14 #define DCCM_ADDR 80040000
15 #define DCCM_SIZE DT_SIZE_K(256)
/Zephyr-latest/soc/altr/qemu_nios2/
Dlinker.ld14 #define _RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
15 #define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
17 #define _ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
18 #define _ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-latest/soc/altr/zephyr_nios2f/
Dlinker.ld14 #define _RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
15 #define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
17 #define _ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
18 #define _ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-latest/boards/snps/nsim/arc_classic/
Dnsim_nsim_em11d.dts11 #define XCCM_ADDR c0000000
12 #define XCCM_SIZE DT_SIZE_K(64)
13 #define YCCM_ADDR e0000000
14 #define YCCM_SIZE DT_SIZE_K(64)
Dnsim-ccm-mem.dtsi11 #define ICCM_ADDR 0
15 #define ICCM_SIZE DT_SIZE_M(1)
19 #define DCCM_ADDR 80000000
23 #define DCCM_SIZE DT_SIZE_M(1)
Dnsim_nsim_vpx5.dts9 #define ICCM_SIZE DT_SIZE_K(256)
10 #define DCCM_SIZE DT_SIZE_K(256)
11 #define UART0_IRQ_NUM 23
/Zephyr-latest/soc/snps/emsdp/
Dlinker.ld19 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
20 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
27 #define ICCM_START DT_REG_ADDR(DT_INST(0, arc_iccm))
28 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
37 #define DCCM_START DT_REG_ADDR(DT_INST(0, arc_dccm))
38 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-latest/soc/snps/emsk/
Dlinker.ld21 #define SRAM_START DT_REG_ADDR(DT_NODELABEL(ddr0))
22 #define SRAM_SIZE DT_REG_SIZE(DT_NODELABEL(ddr0))
28 #define ICCM_START DT_REG_ADDR(DT_INST(0, arc_iccm))
29 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
38 #define DCCM_START DT_REG_ADDR(DT_INST(0, arc_dccm))
39 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-latest/soc/snps/qemu_arc/
Dlinker.ld14 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
15 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
23 #define FLASH_START DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
24 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-latest/include/zephyr/arch/x86/
Dmemory.ld28 #define ARCH_X86_MEMORY_LD
35 #define PHYS_RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
36 #define PHYS_RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
43 #define KERNEL_BASE_ADDR (CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_OFFSET)
44 #define KERNEL_RAM_SIZE (CONFIG_KERNEL_VM_SIZE - CONFIG_KERNEL_VM_OFFSET)
45 #define PHYS_RAM_AVAIL (PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)
47 #define KERNEL_BASE_ADDR (PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)
48 #define KERNEL_RAM_SIZE (PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)
54 #define ROM_END_OFFSET CONFIG_ROM_END_OFFSET
56 #define ROM_END_OFFSET 0
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/Zephyr-latest/include/zephyr/arch/riscv/common/
Dlinker.ld23 #define ROMABLE_REGION ROM
25 #define ROMABLE_REGION RAM
27 #define RAMABLE_REGION RAM
29 #define _EXCEPTION_SECTION_NAME exceptions
30 #define _RESET_SECTION_NAME reset
33 #define ROM_END_OFFSET CONFIG_ROM_END_OFFSET
35 #define ROM_END_OFFSET 0
39 #define FLASH_LOAD_OFFSET CONFIG_FLASH_LOAD_OFFSET
41 #define FLASH_LOAD_OFFSET 0
47 #define ROM_SIZE (CONFIG_FLASH_LOAD_SIZE - ROM_END_OFFSET)
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/Zephyr-latest/include/zephyr/arch/arm64/scripts/
Dlinker.ld23 #define ROMABLE_REGION FLASH
25 #define ROMABLE_REGION RAM
27 #define RAMABLE_REGION RAM
30 #define ROM_ADDR RAM_ADDR
32 #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)
36 #define ROM_END_OFFSET CONFIG_ROM_END_OFFSET
38 #define ROM_END_OFFSET 0
42 #define ROM_SIZE (CONFIG_FLASH_LOAD_SIZE - ROM_END_OFFSET)
44 #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET - ROM_END_OFFSET)
47 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)
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/Zephyr-latest/soc/andestech/ae350/
Dlinker.ld24 #define ROMABLE_REGION ROM
26 #define ROMABLE_REGION RAM
28 #define RAMABLE_REGION RAM
30 #define _EXCEPTION_SECTION_NAME exceptions
31 #define _RESET_SECTION_NAME reset
36 #define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \
39 #define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
41 #define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
47 #define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))
48 #define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)
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/Zephyr-latest/include/zephyr/arch/x86/ia32/scripts/
Dshared_kernel_pages.ld37 #define GDT_NUM_TLS_ENTRIES 1
39 #define GDT_NUM_TLS_ENTRIES 0
43 #define GDT_NUM_ENTRIES 7
45 #define GDT_NUM_ENTRIES 5
47 #define GDT_NUM_ENTRIES 3

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