Searched refs:clk_rate (Results 1 – 13 of 13) sorted by relevance
| /Zephyr-latest/samples/boards/espressif/xt_wdt/src/ |
| D | main.c | 30 uint32_t clk_rate = 0; in main() local
45 &clk_rate); in main()
47 LOG_INF("Current RTC SLOW clock rate: %d Hz", clk_rate); in main()
64 &clk_rate); in main()
66 LOG_INF("Current RTC SLOW clock rate: %d Hz", clk_rate); in main()
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| /Zephyr-latest/drivers/usb/device/ |
| D | usb_dc_dw_stm32.h | 31 uint32_t clk_rate; in clk_enable_st_stm32f4_fsotg() local
42 &clk_rate); in clk_enable_st_stm32f4_fsotg()
47 if (clk_rate != MHZ(48)) { in clk_enable_st_stm32f4_fsotg()
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| /Zephyr-latest/drivers/sdhc/ |
| D | sdhc_cdns.c | 31 uint32_t clk_rate; member
151 if (sdhc_config->clk_rate == 0U) { in sdhc_cdns_init()
158 sdhc_config->clkid, &data->params.clk_rate); in sdhc_cdns_init()
164 data->params.clk_rate = sdhc_config->clk_rate; in sdhc_cdns_init()
250 .clk_rate = DT_INST_PROP(inst, clock_frequency), \
255 .clk_rate = 0, \
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| D | sdhc_cdns_ll.c | 365 sdclkfsval = (cdns_params.clk_rate / 2000) / clk; in sdhc_cdns_host_set_clk()
783 (params->clk_rate > 0) && in sdhc_cdns_sdmmc_init()
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| D | sdhc_cdns_ll.h | 473 int clk_rate; member
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_rcar.c | 62 uint32_t clk_rate; member
212 *cycles = data->clk_rate >> diviser; in pwm_rcar_get_cycles_per_sec()
237 &data->clk_rate); in pwm_rcar_init()
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| /Zephyr-latest/drivers/usb/udc/ |
| D | udc_dwc2_vendor_quirks.h | 39 uint32_t clk_rate; in stm32f4_fsotg_enable_clk() local
50 &clk_rate); in stm32f4_fsotg_enable_clk()
55 if (clk_rate != MHZ(48)) { in stm32f4_fsotg_enable_clk()
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| /Zephyr-latest/drivers/ethernet/eth_nxp_enet_qos/ |
| D | eth_nxp_enet_qos_mac.c | 369 struct nxp_enet_qos_mac_data *data, uint32_t clk_rate) in enet_qos_mac_config_init() argument
391 (clk_rate / USEC_PER_SEC) - 1); in enet_qos_mac_config_init()
521 uint32_t clk_rate; in eth_nxp_enet_qos_mac_init() local
525 ret = clock_control_get_rate(module_cfg->clock_dev, module_cfg->clock_subsys, &clk_rate); in eth_nxp_enet_qos_mac_init()
569 enet_qos_mac_config_init(base, data, clk_rate); in eth_nxp_enet_qos_mac_init()
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| /Zephyr-latest/drivers/serial/ |
| D | uart_rcar.c | 34 uint32_t clk_rate; member
144 reg_val = data->clk_rate / (2 * (HSSRR_SRCYC_DEF_VAL + 1) * baud_rate) - 1; in uart_rcar_set_baudrate()
146 reg_val = ((data->clk_rate + 16 * baud_rate) / (32 * baud_rate) - 1); in uart_rcar_set_baudrate()
308 &data->clk_rate); in uart_rcar_init()
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| D | uart_lpc11u6x.c | 494 uint32_t clk_rate; in lpc11u6x_uartx_config_baud() local
499 &clk_rate); in lpc11u6x_uartx_config_baud()
501 div = clk_rate / (16 * baudrate); in lpc11u6x_uartx_config_baud()
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| /Zephyr-latest/drivers/flash/ |
| D | flash_cadence_qspi_nor.c | 147 .clk_rate = DT_INST_PROP(inst, clock_frequency),\
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| D | flash_cadence_qspi_nor_ll.h | 168 int clk_rate; member
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| D | flash_cadence_qspi_nor_ll.c | 653 cad_qspi_calibration(cad_params, qspi_desired_clk_freq, cad_params->clk_rate); in cad_qspi_init()
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