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/trusted-firmware-a-latest/plat/mediatek/drivers/spm/mt8188/constraints/
Dmt_spm_rc_cpu_buck_ldo.c66 const struct rc_common_state *st = (const struct rc_common_state *)val; in update_rc_status() local
68 if (st == NULL) { in update_rc_status()
72 if ((st->type == CONSTRAINT_UPDATE_VALID) && st->value) { in update_rc_status()
73 if ((st->id == MT_RM_CONSTRAINT_ID_ALL) || in update_rc_status()
74 (st->id == MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO)) { in update_rc_status()
75 struct constraint_status *con = (struct constraint_status *)st->value; in update_rc_status()
77 if ((st->act & MT_LPM_SMC_ACT_CLR) > 0U) { in update_rc_status()
157 struct rc_common_state *st = (struct rc_common_state *)priv; in spm_get_status_rc_cpu_buck_ldo() local
159 if (st == NULL) { in spm_get_status_rc_cpu_buck_ldo()
163 if ((st->id == MT_RM_CONSTRAINT_ID_ALL) || in spm_get_status_rc_cpu_buck_ldo()
[all …]
Dmt_spm_rc_dram.c159 const struct rc_common_state *st; in update_rc_status() local
161 st = (const struct rc_common_state *)val; in update_rc_status()
163 if (st == NULL) { in update_rc_status()
167 if (st->type == CONSTRAINT_UPDATE_COND_CHECK) { in update_rc_status()
170 spm_rc_condition_modifier(st->id, st->act, st->value, in update_rc_status()
172 } else if ((st->type == CONSTRAINT_UPDATE_VALID) || in update_rc_status()
173 (st->type == CONSTRAINT_RESIDNECY)) { in update_rc_status()
174 spm_rc_constraint_status_set(st->id, st->type, st->act, in update_rc_status()
176 (struct constraint_status * const)st->value, in update_rc_status()
179 INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type); in update_rc_status()
[all …]
Dmt_spm_rc_syspll.c202 const struct rc_common_state *st; in update_rc_status() local
204 st = (const struct rc_common_state *)val; in update_rc_status()
206 if (st == NULL) { in update_rc_status()
210 if (st->type == CONSTRAINT_UPDATE_COND_CHECK) { in update_rc_status()
213 spm_rc_condition_modifier(st->id, st->act, st->value, in update_rc_status()
215 } else if ((st->type == CONSTRAINT_UPDATE_VALID) || in update_rc_status()
216 (st->type == CONSTRAINT_RESIDNECY)) { in update_rc_status()
217 spm_rc_constraint_status_set(st->id, st->type, st->act, in update_rc_status()
219 (struct constraint_status * const)st->value, in update_rc_status()
222 INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type); in update_rc_status()
[all …]
Dmt_spm_rc_bus26m.c253 const struct rc_common_state *st; in update_rc_status() local
255 st = (const struct rc_common_state *)val; in update_rc_status()
257 if (st == NULL) { in update_rc_status()
261 if (st->type == CONSTRAINT_UPDATE_COND_CHECK) { in update_rc_status()
264 spm_rc_condition_modifier(st->id, st->act, st->value, in update_rc_status()
266 } else if ((st->type == CONSTRAINT_UPDATE_VALID) || in update_rc_status()
267 (st->type == CONSTRAINT_RESIDNECY)) { in update_rc_status()
268 spm_rc_constraint_status_set(st->id, st->type, st->act, in update_rc_status()
270 (struct constraint_status * const)st->value, in update_rc_status()
273 INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type); in update_rc_status()
[all …]
/trusted-firmware-a-latest/plat/st/stm32mp2/
Dplatform.mk7 include plat/st/common/common.mk
35 STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S
36 STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S
43 PLAT_INCLUDES += -Iplat/st/stm32mp2/include/
46 PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
47 PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
49 BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
50 BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c
52 include plat/st/common/common_rules.mk
/trusted-firmware-a-latest/fdts/
Dstm32mp135f-dk.dts4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
17 compatible = "st,stm32mp135f-dk", "st,stm32mp135";
55 st,non-secure-otp;
77 compatible = "st,stpmic1";
84 compatible = "st,stpmic1-regulators";
118 st,mask-reset;
188 st,clksrc = <
206 st,clkdiv = <
218 st,pll_vco {
244 pll1:st,pll@0 {
[all …]
Dstm32mp15-ddr.dtsi7 st,mem-name = DDR_MEM_NAME;
8 st,mem-speed = <DDR_MEM_SPEED>;
9 st,mem-size = <DDR_MEM_SIZE>;
11 st,ctl-reg = <
39 st,ctl-timing = <
54 st,ctl-map = <
66 st,ctl-perf = <
86 st,phy-reg = <
100 st,phy-timing = <
Dstm32mp151.dtsi4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
82 compatible = "st,stm32-timers";
90 compatible = "st,stm32h7-uart";
99 compatible = "st,stm32h7-uart";
108 compatible = "st,stm32h7-uart";
118 compatible = "st,stm32h7-uart";
127 compatible = "st,stm32mp15-i2c";
136 st,syscfg-fmp = <&syscfg 0x4 0x2>;
142 compatible = "st,stm32h7-uart";
151 compatible = "st,stm32h7-uart";
[all …]
Dstm32mp157c-ed1.dts4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
36 st,non-secure-otp;
41 st,digbypass;
69 compatible = "st,stpmic1";
77 compatible = "st,stpmic1-regulators";
109 st,mask-reset;
139 st,regulator-sink-source;
193 st,clksrc = <
205 st,clkdiv = <
[all …]
Dstm32mp157a-avenger96.dts20 compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
46 compatible = "st,stpmic1";
53 st,main-control-register = <0x04>;
54 st,vin-control-register = <0xc0>;
55 st,usb-control-register = <0x30>;
58 compatible = "st,stpmic1-regulators";
90 st,mask-reset;
120 st,regulator-sink-source;
174 st,clksrc = <
186 st,clkdiv = <
[all …]
Dstm32mp131.dtsi4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
82 compatible = "st,stm32h7-uart";
91 compatible = "st,stm32h7-uart";
100 compatible = "st,stm32h7-uart";
109 compatible = "st,stm32h7-uart";
118 compatible = "st,stm32h7-uart";
127 compatible = "st,stm32h7-uart";
136 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
152 compatible = "st,stm32h7-uart";
161 compatible = "st,stm32h7-uart";
[all …]
Dstm32mp251.dtsi4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
88 compatible = "st,stm32mp25-rifsc";
94 compatible = "st,stm32h7-uart";
103 compatible = "st,stm32mp25-rcc";
110 compatible = "st,stm32mp25-pwr";
135 compatible = "st,stm32mp25-syscfg", "syscon";
142 compatible = "st,stm32mp257-pinctrl";
153 st,bank-name = "GPIOA";
164 st,bank-name = "GPIOB";
175 st,bank-name = "GPIOC";
[all …]
Dstm32mp15xx-osd32.dtsi18 compatible = "st,stpmic1";
25 compatible = "st,stpmic1-regulators";
54 st,mask-reset;
86 st,regulator-sink-source;
130 compatible = "st,stpmic1-wdt";
162 st,non-secure-otp;
167 st,digbypass;
184 st,clksrc = <
196 st,clkdiv = <
210 st,pkcs = <
[all …]
Dstm32mp15xx-dkx.dtsi4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
34 st,non-secure-otp;
39 st,digbypass;
63 compatible = "st,stpmic1";
71 compatible = "st,stpmic1-regulators";
110 st,mask-reset;
142 st,regulator-sink-source;
197 st,clksrc = <
209 st,clkdiv = <
223 st,pkcs = <
[all …]
Dstm32mp157c-odyssey-som.dtsi33 st,non-secure-otp;
38 st,digbypass;
66 compatible = "st,stpmic1";
74 compatible = "st,stpmic1-regulators";
113 st,mask-reset;
145 st,regulator-sink-source;
189 compatible = "st,stpmic1-wdt";
206 st,clksrc = <
218 st,clkdiv = <
232 st,pkcs = <
[all …]
Dstm32mp15xx-dhcom-som.dtsi23 st,non-secure-otp;
47 compatible = "st,stpmic1";
55 compatible = "st,stpmic1-regulators";
87 st,mask-reset;
118 st,regulator-sink-source;
192 st,clksrc = <
204 st,clkdiv = <
218 st,pkcs = <
257 pll1: st,pll@0 {
258 compatible = "st,stm32mp1-pll";
[all …]
Dstm32mp13-ddr.dtsi7 st,mem-name = DDR_MEM_NAME;
8 st,mem-speed = <DDR_MEM_SPEED>;
9 st,mem-size = <DDR_MEM_SIZE>;
11 st,ctl-reg = <
39 st,ctl-timing = <
54 st,ctl-map = <
66 st,ctl-perf = <
80 st,phy-reg = <
92 st,phy-timing = <
Dstm32mp151a-prtt1a.dts16 compatible = "prt,prtt1a", "st,stm32mp151";
69 st,clksrc = <
81 st,clkdiv = <
95 st,pkcs = <
134 pll1: st,pll@0 {
135 compatible = "st,stm32mp1-pll";
142 pll2: st,pll@1 {
143 compatible = "st,stm32mp1-pll";
150 pll3: st,pll@2 {
151 compatible = "st,stm32mp1-pll";
[all …]
Dstm32mp15xx-dhcor-som.dtsi42 compatible = "st,stpmic1";
50 compatible = "st,stpmic1-regulators";
111 st,regulator-sink-source;
187 st,clksrc = <
199 st,clkdiv = <
213 st,pkcs = <
252 pll1: st,pll@0 {
253 compatible = "st,stm32mp1-pll";
260 pll2: st,pll@1 {
261 compatible = "st,stm32mp1-pll";
[all …]
Dstm32mp157a-dk1.dts4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
16 compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
/trusted-firmware-a-latest/plat/st/stm32mp1/sp_min/
Dsp_min-stm32mp1.mk19 BL32_SOURCES += drivers/st/etzpc/etzpc.c \
21 plat/st/stm32mp1/sp_min/sp_min_setup.c \
22 plat/st/stm32mp1/stm32mp1_pm.c \
23 plat/st/stm32mp1/stm32mp1_shared_resources.c \
24 plat/st/stm32mp1/stm32mp1_topology.c
35 plat/st/common/stm32mp_gic.c
48 BL32_SOURCES += plat/st/stm32mp1/services/bsec_svc.c \
49 plat/st/stm32mp1/services/stm32mp1_svc_setup.c \
50 plat/st/stm32mp1/stm32mp1_scmi.c
/trusted-firmware-a-latest/drivers/rpi3/mailbox/
Drpi3_mbox.c24 uint32_t st, data; in rpi3_vc_mailbox_request_send() local
38 st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET); in rpi3_vc_mailbox_request_send()
46 } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U); in rpi3_vc_mailbox_request_send()
56 st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET); in rpi3_vc_mailbox_request_send()
64 } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U); in rpi3_vc_mailbox_request_send()
/trusted-firmware-a-latest/plat/rockchip/px30/drivers/secure/
Dsecure.c22 uintptr_t st, size_t sz) in secure_ddr_region() argument
24 uintptr_t ed = st + sz; in secure_ddr_region()
29 assert(st < ed); in secure_ddr_region()
32 assert(st % SIZE_M(1) == 0); in secure_ddr_region()
35 st_mb = st / SIZE_M(1); in secure_ddr_region()
/trusted-firmware-a-latest/plat/mediatek/drivers/cirq/
Dmt_cirq.c301 uint32_t addr, st, val; in mt_irq_get_en() local
304 st = mmio_read_32(addr); in mt_irq_get_en()
306 val = (st >> (irq % 32U)) & 1U; in mt_irq_get_en()
450 uint32_t st; in mt_cirq_enable() local
455 st = mmio_read_32(CIRQ_CON); in mt_cirq_enable()
459 st |= (CIRQ_CON_EN << CIRQ_CON_EN_BITS); in mt_cirq_enable()
461 mmio_write_32(CIRQ_CON, (st & CIRQ_CON_BITS_MASK)); in mt_cirq_enable()
469 uint32_t st; in mt_cirq_disable() local
471 st = mmio_read_32(CIRQ_CON); in mt_cirq_disable()
472 st &= ~(CIRQ_CON_EN << CIRQ_CON_EN_BITS); in mt_cirq_disable()
[all …]
/trusted-firmware-a-latest/plat/rockchip/rk3288/drivers/secure/
Dsecure.c50 static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, size_t sz) in sgrf_ddr_rgn_config() argument
52 uintptr_t ed = st + sz; in sgrf_ddr_rgn_config()
56 assert(st < ed); in sgrf_ddr_rgn_config()
59 assert(st % SIZE_M(1) == 0); in sgrf_ddr_rgn_config()
62 st_mb = st / SIZE_M(1); in sgrf_ddr_rgn_config()

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