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Searched refs:idx (Results 1 – 25 of 100) sorted by relevance

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/trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/mcdi/
Dmt_lp_irqremain.c68 uint32_t idx; in mt_lp_irqremain_init() local
73 idx = remain_irqs.count; in mt_lp_irqremain_init()
74 remain_irqs.irqs[idx] = EDMA0_IRQ_ID; in mt_lp_irqremain_init()
75 remain_irqs.wakeupsrc_cat[idx] = 0; in mt_lp_irqremain_init()
76 remain_irqs.wakeupsrc[idx] = 0; in mt_lp_irqremain_init()
80 idx = remain_irqs.count; in mt_lp_irqremain_init()
81 remain_irqs.irqs[idx] = MDLA_IRQ_ID; in mt_lp_irqremain_init()
82 remain_irqs.wakeupsrc_cat[idx] = 0; in mt_lp_irqremain_init()
83 remain_irqs.wakeupsrc[idx] = 0; in mt_lp_irqremain_init()
87 idx = remain_irqs.count; in mt_lp_irqremain_init()
[all …]
/trusted-firmware-a-latest/plat/imx/imx8m/
Dimx8m_csu.c19 val = mmio_read_32(CSLx_REG(csu->idx)); in imx_csu_init()
20 if (val & CSLx_LOCK(csu->idx)) { in imx_csu_init()
23 mmio_clrsetbits_32(CSLx_REG(csu->idx), CSLx_CFG(0xff, csu->idx), in imx_csu_init()
24 CSLx_CFG(csu->csl_level | (csu->lock << 8), csu->idx)); in imx_csu_init()
27 val = mmio_read_32(CSU_HP_REG(csu->idx)); in imx_csu_init()
28 if (val & CSU_HP_LOCK(csu->idx)) { in imx_csu_init()
31 mmio_clrsetbits_32(CSU_HP_REG(csu->idx), CSU_HP_CFG(0x1, csu->idx), in imx_csu_init()
32 CSU_HP_CFG(csu->hp | (csu->lock << 0x1), csu->idx)); in imx_csu_init()
35 val = mmio_read_32(CSU_SA_REG(csu->idx)); in imx_csu_init()
36 if (val & CSU_SA_LOCK(csu->idx)) { in imx_csu_init()
[all …]
/trusted-firmware-a-latest/lib/extensions/amu/
Damu_private.h23 uint64_t amu_group0_cnt_read_internal(unsigned int idx);
24 void amu_group0_cnt_write_internal(unsigned int idx, uint64_t val);
26 uint64_t amu_group1_cnt_read_internal(unsigned int idx);
27 void amu_group1_cnt_write_internal(unsigned int idx, uint64_t val);
28 void amu_group1_set_evtype_internal(unsigned int idx, unsigned int val);
31 uint64_t amu_group0_voffset_read_internal(unsigned int idx);
32 void amu_group0_voffset_write_internal(unsigned int idx, uint64_t val);
34 uint64_t amu_group1_voffset_read_internal(unsigned int idx);
35 void amu_group1_voffset_write_internal(unsigned int idx, uint64_t val);
/trusted-firmware-a-latest/drivers/st/ddr/
Dstm32mp_ram.c46 uint32_t idx; in stm32mp_ddr_dt_get_param() local
48 for (idx = 0U; idx < param_size; idx++) { in stm32mp_ddr_dt_get_param()
49 ret = fdt_read_uint32_array(fdt, node, param[idx].name, param[idx].size, in stm32mp_ddr_dt_get_param()
50 (void *)(config + param[idx].offset)); in stm32mp_ddr_dt_get_param()
52 VERBOSE("%s: %s[0x%x] = %d\n", __func__, param[idx].name, param[idx].size, ret); in stm32mp_ddr_dt_get_param()
54 ERROR("%s: Cannot read %s, error=%d\n", __func__, param[idx].name, ret); in stm32mp_ddr_dt_get_param()
/trusted-firmware-a-latest/bl31/
Dehf.c34 #define PRI_BIT(idx) (((ehf_pri_bits_t) 1u) << (idx)) argument
40 #define IDX_TO_PRI(idx) \ argument
41 ((((unsigned) idx) << (7u - exception_data.pri_bits)) & 0x7fU)
44 #define IS_IDX_VALID(idx) \ argument
45 ((exception_data.ehf_priorities[idx].ehf_handler & EHF_PRI_VALID_) != 0U)
56 unsigned int idx; in pri_to_idx() local
58 idx = EHF_PRI_TO_IDX(priority, exception_data.pri_bits); in pri_to_idx()
59 assert(idx < exception_data.num_priorities); in pri_to_idx()
60 assert(IS_IDX_VALID(idx)); in pri_to_idx()
62 return idx; in pri_to_idx()
[all …]
/trusted-firmware-a-latest/plat/marvell/armada/common/
Dmarvell_gicv2.c35 #define A7K8K_ODMI_PMU_IRQ(idx) ((2 + idx) << 12) argument
37 #define A7K8K_ODMI_PMU_GIC_IRQ(idx) (130 + idx) argument
79 unsigned int idx = plat_my_core_pos(); in a7k8k_pmu_interrupt_handler() local
98 mmio_write_32(A7K8K_ODMIN_SET_REG, A7K8K_ODMI_PMU_IRQ(idx)); in a7k8k_pmu_interrupt_handler()
107 unsigned int idx; in mvebu_pmu_interrupt_enable() local
117 for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) in mvebu_pmu_interrupt_enable()
118 gicv2_interrupt_set_cfg(A7K8K_ODMI_PMU_GIC_IRQ(idx), in mvebu_pmu_interrupt_enable()
/trusted-firmware-a-latest/lib/gpt_rme/
Dgpt_rme.c169 unsigned int idx; in gpt_validate_pas_mappings() local
177 for (idx = 0U; idx < pas_region_cnt; idx++) { in gpt_validate_pas_mappings()
179 if ((ULONG_MAX - pas_regions[idx].base_pa) < in gpt_validate_pas_mappings()
180 pas_regions[idx].size) { in gpt_validate_pas_mappings()
181 ERROR("[GPT] Address overflow in PAS[%u]!\n", idx); in gpt_validate_pas_mappings()
186 if (((pas_regions[idx].base_pa + pas_regions[idx].size) > in gpt_validate_pas_mappings()
188 !gpt_is_gpi_valid(GPT_PAS_ATTR_GPI(pas_regions[idx].attrs))) { in gpt_validate_pas_mappings()
189 ERROR("[GPT] PAS[%u] is invalid!\n", idx); in gpt_validate_pas_mappings()
198 for (unsigned int i = idx + 1; i < pas_region_cnt; i++) { in gpt_validate_pas_mappings()
199 if (gpt_check_pas_overlap(pas_regions[idx].base_pa, in gpt_validate_pas_mappings()
[all …]
/trusted-firmware-a-latest/include/lib/extensions/
Dras_arch.h198 static inline uint64_t ser_get_feature(uintptr_t base, unsigned int idx) in ser_get_feature() argument
200 return mmio_read_64(base + ERR_FR(idx)); in ser_get_feature()
203 static inline uint64_t ser_get_control(uintptr_t base, unsigned int idx) in ser_get_control() argument
205 return mmio_read_64(base + ERR_CTLR(idx)); in ser_get_control()
208 static inline uint64_t ser_get_status(uintptr_t base, unsigned int idx) in ser_get_status() argument
210 return mmio_read_64(base + ERR_STATUS(idx)); in ser_get_status()
224 static inline void ser_set_status(uintptr_t base, unsigned int idx, in ser_set_status() argument
227 mmio_write_64(base + ERR_STATUS(idx), status); in ser_set_status()
230 static inline uint64_t ser_get_addr(uintptr_t base, unsigned int idx) in ser_get_addr() argument
232 return mmio_read_64(base + ERR_ADDR(idx)); in ser_get_addr()
[all …]
/trusted-firmware-a-latest/lib/extensions/amu/aarch64/
Damu.c283 static uint64_t amu_group0_cnt_read(unsigned int idx) in amu_group0_cnt_read() argument
286 assert(idx < read_amcgcr_el0_cg0nc()); in amu_group0_cnt_read()
288 return amu_group0_cnt_read_internal(idx); in amu_group0_cnt_read()
292 static void amu_group0_cnt_write(unsigned int idx, uint64_t val) in amu_group0_cnt_write() argument
295 assert(idx < read_amcgcr_el0_cg0nc()); in amu_group0_cnt_write()
297 amu_group0_cnt_write_internal(idx, val); in amu_group0_cnt_write()
307 static bool amu_group0_voffset_supported(uint64_t idx) in amu_group0_voffset_supported() argument
309 switch (idx) { in amu_group0_voffset_supported()
320 "architected counter %" PRIu64 "!\n", idx); in amu_group0_voffset_supported()
332 static uint64_t amu_group0_voffset_read(unsigned int idx) in amu_group0_voffset_read() argument
[all …]
/trusted-firmware-a-latest/drivers/arm/rss/
Drss_comms.c83 size_t idx; in psa_call() local
105 for (idx = 0; idx < in_len; idx++) { in psa_call()
106 VERBOSE("in_vec[%lu].len=%lu\n", idx, in_vec[idx].len); in psa_call()
107 VERBOSE("in_vec[%lu].buf=%p\n", idx, (void *)in_vec[idx].base); in psa_call()
140 for (idx = 0U; idx < out_len; idx++) { in psa_call()
141 VERBOSE("out_vec[%lu].len=%lu\n", idx, out_vec[idx].len); in psa_call()
142 VERBOSE("out_vec[%lu].buf=%p\n", idx, (void *)out_vec[idx].base); in psa_call()
/trusted-firmware-a-latest/tools/cert_create/src/
Dcmd_opt.c43 const char *cmd_opt_get_name(int idx) in cmd_opt_get_name() argument
45 if (idx >= num_reg_opt) { in cmd_opt_get_name()
49 return long_opt[idx].name; in cmd_opt_get_name()
52 const char *cmd_opt_get_help_msg(int idx) in cmd_opt_get_help_msg() argument
54 if (idx >= num_reg_opt) { in cmd_opt_get_help_msg()
58 return help_msg[idx]; in cmd_opt_get_help_msg()
/trusted-firmware-a-latest/tools/encrypt_fw/src/
Dcmd_opt.c43 const char *cmd_opt_get_name(int idx) in cmd_opt_get_name() argument
45 if (idx >= num_reg_opt) { in cmd_opt_get_name()
49 return long_opt[idx].name; in cmd_opt_get_name()
52 const char *cmd_opt_get_help_msg(int idx) in cmd_opt_get_help_msg() argument
54 if (idx >= num_reg_opt) { in cmd_opt_get_help_msg()
58 return help_msg[idx]; in cmd_opt_get_help_msg()
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/spm/
Dmt_spm_pmic_wrap.c102 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
126 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, in mt_spm_pmic_wrap_set_cmd() argument
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
144 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/spm/
Dmt_spm_pmic_wrap.c113 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
125 for (idx = 0; idx < pw->set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
126 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
127 data = pw->set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
128 mmio_write_32(pw->addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
134 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, in mt_spm_pmic_wrap_set_cmd() argument
143 if (pw == NULL || idx >= pw->set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
147 pw->set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
151 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
152 mmio_write_32(pw->addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/spm/
Dmt_spm_pmic_wrap.c102 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
126 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, in mt_spm_pmic_wrap_set_cmd() argument
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
144 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
[all …]
/trusted-firmware-a-latest/plat/mediatek/drivers/spm/mt8188/
Dmt_spm_pmic_wrap.c107 int idx; in mt_spm_pmic_wrap_set_phase() local
120 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
121 mmio_write_32(pw.addr[idx].cmd_addr, in mt_spm_pmic_wrap_set_phase()
122 (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | in mt_spm_pmic_wrap_set_phase()
123 (pw.set[phase]._[idx].cmd_wdata)); in mt_spm_pmic_wrap_set_phase()
127 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx, in mt_spm_pmic_wrap_set_cmd() argument
131 if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) { in mt_spm_pmic_wrap_set_cmd()
135 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
139 mmio_write_32(pw.addr[idx].cmd_addr, in mt_spm_pmic_wrap_set_cmd()
140 (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
[all …]
/trusted-firmware-a-latest/plat/brcm/board/stingray/src/
Diommu.c308 uint32_t idx = smmu->cfg[index].cbndx; in arm_smmu_smr_cfg() local
316 ARM_SMMU_GR0_SMR(idx)), reg); in arm_smmu_smr_cfg()
321 uint32_t idx = smmu->cfg[index].cbndx; in arm_smmu_s2cr_cfg() local
329 ARM_SMMU_GR0_S2CR(idx)), reg); in arm_smmu_s2cr_cfg()
404 uint32_t idx; in arm_smmu_create_identity_map() local
441 for (idx = 0; idx < smmu->streams; idx++) { in arm_smmu_create_identity_map()
443 smmu->s2cr[idx].type = S2CR_TYPE_TRANS; in arm_smmu_create_identity_map()
444 smmu->s2cr[idx].privcfg = S2CR_PRIVCFG_DEFAULT; in arm_smmu_create_identity_map()
445 smmu->s2cr[idx].cbndx = context_bank_index; in arm_smmu_create_identity_map()
446 smmu->cfg[idx].cbndx = context_bank_index; in arm_smmu_create_identity_map()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/mcdi/
Dmt_lp_irqremain.c57 uint32_t idx; in mt_lp_irqremain_init() local
62 idx = remain_irqs.count; in mt_lp_irqremain_init()
63 remain_irqs.irqs[idx] = KEYPAD_IRQ_ID; in mt_lp_irqremain_init()
64 remain_irqs.wakeupsrc_cat[idx] = 0; in mt_lp_irqremain_init()
65 remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC; in mt_lp_irqremain_init()
/trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/spm/
Dspm_pmic_wrap.c117 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
132 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
133 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
134 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
135 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
139 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, in mt_spm_pmic_wrap_set_cmd() argument
147 if (idx >= pw.set[phase].nr_idx) in mt_spm_pmic_wrap_set_cmd()
150 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
155 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
156 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
[all …]
/trusted-firmware-a-latest/lib/fconf/
Dfconf_amu_getter.c38 uintptr_t idx = 0U; in fconf_populate_amu_cpu_amu() local
45 ret = fdt_get_reg_props_by_index(fdt, node, 0, &idx, NULL); in fconf_populate_amu_cpu_amu()
56 amu->enable |= (1 << idx); in fconf_populate_amu_cpu_amu()
76 int idx; in fconf_populate_amu_cpu() local
95 idx = plat_core_pos_by_mpidr(mpidr); in fconf_populate_amu_cpu()
96 if (idx < 0) { in fconf_populate_amu_cpu()
100 amu = &fconf_amu_topology_.cores[idx]; in fconf_populate_amu_cpu()
/trusted-firmware-a-latest/drivers/auth/
Dimg_parser_mod.c69 unsigned int idx; in img_parser_check_integrity() local
80 idx = parser_lib_indices[img_type]; in img_parser_check_integrity()
81 assert(idx != INVALID_IDX); in img_parser_check_integrity()
84 return parser_lib_descs[idx].check_integrity(img_ptr, img_len); in img_parser_check_integrity()
103 unsigned int idx; in img_parser_get_auth_param() local
120 idx = parser_lib_indices[img_type]; in img_parser_get_auth_param()
121 assert(idx != INVALID_IDX); in img_parser_get_auth_param()
124 return parser_lib_descs[idx].get_auth_param(type_desc, img_ptr, img_len, in img_parser_get_auth_param()
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/mcdi/
Dmt_lp_irqremain.c62 uint32_t idx; in mt_lp_irqremain_init() local
67 idx = remain_irqs.count; in mt_lp_irqremain_init()
68 remain_irqs.irqs[idx] = KEYPAD_IRQ_ID; in mt_lp_irqremain_init()
69 remain_irqs.wakeupsrc_cat[idx] = 0U; in mt_lp_irqremain_init()
70 remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC; in mt_lp_irqremain_init()
/trusted-firmware-a-latest/drivers/st/clk/
Dclk-stm32-core.h174 int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx);
200 unsigned long clk_stm32_divider_recalc(struct stm32_clk_priv *priv, int idx,
203 int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int idx);
204 void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int idx);
207 bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int idx);
224 #define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \ argument
225 [(idx)] = (struct clk_stm32){ \
239 #define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \ argument
240 [(idx)] = (struct clk_stm32){ \
258 #define FIXED_FACTOR(idx, _idx, _parent, _mult, _div) \ argument
[all …]
/trusted-firmware-a-latest/drivers/st/iwdg/
Dstm32_iwdg.c91 uint32_t idx; in stm32_iwdg_init() local
95 idx = stm32_iwdg_get_instance(dt_info.base); in stm32_iwdg_init()
96 iwdg = &stm32_iwdg[idx]; in stm32_iwdg_init()
112 hw_init = stm32_iwdg_get_otp_config(idx); in stm32_iwdg_init()
117 idx + 1U); in stm32_iwdg_init()
137 VERBOSE("IWDG%u found, %ssecure\n", idx + 1U, in stm32_iwdg_init()
148 if (stm32_iwdg_shadow_update(idx, iwdg->flags) != BSEC_OK) { in stm32_iwdg_init()
/trusted-firmware-a-latest/plat/mediatek/common/lpm/
Dmt_lp_rm.c39 int mt_lp_rm_reset_constraint(unsigned int idx, unsigned int cpuid, int stateid) in mt_lp_rm_reset_constraint() argument
43 if ((plat_mt_rm.plat_rm == NULL) || (idx >= plat_mt_rm.count)) { in mt_lp_rm_reset_constraint()
47 rc = plat_mt_rm.plat_rm->consts[idx]; in mt_lp_rm_reset_constraint()
97 int mt_lp_rm_find_constraint(unsigned int idx, unsigned int cpuid, in mt_lp_rm_find_constraint() argument
105 if ((rm == NULL) || (idx >= plat_mt_rm.count)) { in mt_lp_rm_find_constraint()
118 for (i = idx, rc = (rm->consts + idx); *rc != NULL; i++, rc++) { in mt_lp_rm_find_constraint()
129 int mt_lp_rm_find_and_run_constraint(unsigned int idx, unsigned int cpuid, in mt_lp_rm_find_and_run_constraint() argument
134 res = mt_lp_rm_find_constraint(idx, cpuid, stateid, priv); in mt_lp_rm_find_and_run_constraint()

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