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Searched refs:sp (Results 1 – 25 of 121) sorted by relevance

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/Zephyr-latest/arch/nios2/core/
Dexception.S38 subi sp, sp, __struct_arch_esf_SIZEOF
41 stw ra, __struct_arch_esf_ra_OFFSET(sp)
42 stw r1, __struct_arch_esf_r1_OFFSET(sp)
43 stw r2, __struct_arch_esf_r2_OFFSET(sp)
44 stw r3, __struct_arch_esf_r3_OFFSET(sp)
45 stw r4, __struct_arch_esf_r4_OFFSET(sp)
46 stw r5, __struct_arch_esf_r5_OFFSET(sp)
47 stw r6, __struct_arch_esf_r6_OFFSET(sp)
48 stw r7, __struct_arch_esf_r7_OFFSET(sp)
49 stw r8, __struct_arch_esf_r8_OFFSET(sp)
[all …]
Dswap.S26 addi sp, sp, -12
27 stw ra, 8(sp)
28 stw fp, 4(sp)
29 stw r4, 0(sp)
33 ldw r4, 0(sp)
34 ldw fp, 4(sp)
35 ldw ra, 8(sp)
36 addi sp, sp, 12
61 stw sp, _thread_offset_to_sp(r11)
95 ldw sp, _thread_offset_to_sp(r2)
[all …]
/Zephyr-latest/arch/arc/core/dsp/
Dswap_dsp_macros.h17 st_s r13, [sp, ___callee_saved_stack_t_dsp_ctrl_OFFSET]
19 st_s r13, [sp, ___callee_saved_stack_t_acc0_glo_OFFSET]
21 st_s r13, [sp, ___callee_saved_stack_t_acc0_ghi_OFFSET]
24 st_s r13, [sp, ___callee_saved_stack_t_dsp_bfly0_OFFSET]
26 st_s r13, [sp, ___callee_saved_stack_t_dsp_fft_ctrl_OFFSET]
43 st r13, [sp, ___callee_saved_stack_t_agu_ap0_OFFSET]
45 st r13, [sp, ___callee_saved_stack_t_agu_ap1_OFFSET]
47 st r13, [sp, ___callee_saved_stack_t_agu_ap2_OFFSET]
49 st r13, [sp, ___callee_saved_stack_t_agu_ap3_OFFSET]
51 st r13, [sp, ___callee_saved_stack_t_agu_os0_OFFSET]
[all …]
/Zephyr-latest/arch/sparc/core/
Dinterrupt_trap.S65 std %l0, [%sp + 0x00]
66 std %l2, [%sp + 0x08]
67 std %l4, [%sp + 0x10]
68 std %l6, [%sp + 0x18]
69 std %i0, [%sp + 0x20]
70 std %i2, [%sp + 0x28]
71 std %i4, [%sp + 0x30]
72 std %i6, [%sp + 0x38]
90 sub %fp, ISF_SIZE, %sp
98 std %l0, [%sp + ISF_PSR_OFFSET] /* psr pc */
[all …]
Dfault_trap.S59 std %l0, [%sp + 0x00]
60 std %l2, [%sp + 0x08]
61 std %l4, [%sp + 0x10]
62 std %l6, [%sp + 0x18]
63 std %i0, [%sp + 0x20]
64 std %i2, [%sp + 0x28]
65 std %i4, [%sp + 0x30]
66 std %i6, [%sp + 0x38]
75 sub %fp, 96 + __struct_arch_esf_SIZEOF, %sp
84 std %i0, [%sp + 96 + __struct_arch_esf_out_OFFSET + 0x00]
[all …]
Dwindow_trap.S25 std %l0, [%sp + 0x00]
26 std %l2, [%sp + 0x08]
27 std %l4, [%sp + 0x10]
29 std %l6, [%sp + 0x18]
33 std %i0, [%sp + 0x20]
36 std %i2, [%sp + 0x28]
40 std %i4, [%sp + 0x30]
42 std %i6, [%sp + 0x38]
65 ldd [%sp + 0x00], %l0
66 ldd [%sp + 0x08], %l2
[all …]
/Zephyr-latest/arch/arc/include/
Dswap_macros.h26 SUBR sp, sp, ___callee_saved_stack_t_SIZEOF
29 STR r13, sp, ___callee_saved_stack_t_r13_OFFSET
30 STR r14, sp, ___callee_saved_stack_t_r14_OFFSET
31 STR r15, sp, ___callee_saved_stack_t_r15_OFFSET
32 STR r16, sp, ___callee_saved_stack_t_r16_OFFSET
33 STR r17, sp, ___callee_saved_stack_t_r17_OFFSET
34 STR r18, sp, ___callee_saved_stack_t_r18_OFFSET
35 STR r19, sp, ___callee_saved_stack_t_r19_OFFSET
36 STR r20, sp, ___callee_saved_stack_t_r20_OFFSET
37 STR r21, sp, ___callee_saved_stack_t_r21_OFFSET
[all …]
/Zephyr-latest/arch/riscv/core/
Disr.S27 RV_E( op t0, __struct_arch_esf_t0_OFFSET(sp) );\
28 RV_E( op t1, __struct_arch_esf_t1_OFFSET(sp) );\
29 RV_E( op t2, __struct_arch_esf_t2_OFFSET(sp) );\
30 RV_I( op t3, __struct_arch_esf_t3_OFFSET(sp) );\
31 RV_I( op t4, __struct_arch_esf_t4_OFFSET(sp) );\
32 RV_I( op t5, __struct_arch_esf_t5_OFFSET(sp) );\
33 RV_I( op t6, __struct_arch_esf_t6_OFFSET(sp) );\
34 RV_E( op a0, __struct_arch_esf_a0_OFFSET(sp) );\
35 RV_E( op a1, __struct_arch_esf_a1_OFFSET(sp) );\
36 RV_E( op a2, __struct_arch_esf_a2_OFFSET(sp) );\
[all …]
Dfatal.c40 uintptr_t sp = (uintptr_t)esf + sizeof(struct arch_esf); in z_riscv_get_sp_before_exc() local
48 sp = esf->sp; in z_riscv_get_sp_before_exc()
52 return sp; in z_riscv_get_sp_before_exc()
158 uintptr_t sp = (uintptr_t)esf + sizeof(struct arch_esf); in bad_stack_pointer() local
162 sp >= arch_current_thread()->arch.priv_stack_start && in bad_stack_pointer()
163 sp < arch_current_thread()->arch.priv_stack_start + Z_RISCV_STACK_GUARD_SIZE) { in bad_stack_pointer()
168 sp >= arch_current_thread()->stack_info.start - K_THREAD_STACK_RESERVED && in bad_stack_pointer()
169 sp < arch_current_thread()->stack_info.start - K_THREAD_STACK_RESERVED in bad_stack_pointer()
176 if (sp >= arch_current_thread()->stack_info.start - K_KERNEL_STACK_RESERVED && in bad_stack_pointer()
177 sp < arch_current_thread()->stack_info.start - K_KERNEL_STACK_RESERVED in bad_stack_pointer()
[all …]
/Zephyr-latest/arch/arm64/core/
Dvector_table.S40 sub sp, sp, ___esf_t_SIZEOF
48 add sp, sp, x0 // sp' = sp + x0
49 sub x0, sp, x0 // x0' = sp' - x0 = sp
51 stp x16, x17, [sp, -(___esf_t_SIZEOF - ___esf_t_x16_x17_OFFSET)]
52 stp x18, lr, [sp, -(___esf_t_SIZEOF - ___esf_t_x18_lr_OFFSET)]
57 stp x0, x1, [sp, ___esf_t_x0_x1_OFFSET]
58 stp x2, x3, [sp, ___esf_t_x2_x3_OFFSET]
59 stp x4, x5, [sp, ___esf_t_x4_x5_OFFSET]
60 stp x6, x7, [sp, ___esf_t_x6_x7_OFFSET]
61 stp x8, x9, [sp, ___esf_t_x8_x9_OFFSET]
[all …]
Dswitch.S52 mov x4, sp
72 stp x0, x1, [sp, #-16]!
74 ldp x0, x1, [sp], #16
109 mov sp, x4
119 str lr, [sp, #-16]!
121 ldr lr, [sp], #16
125 str lr, [sp, #-16]!
127 ldr lr, [sp], #16
150 mov x0, sp
180 ldp x1, x0, [sp, ___esf_t_x0_x1_OFFSET]
[all …]
Disr_wrapper.S44 mov x2, sp
45 mov sp, x1
46 str x2, [sp, #-16]!
85 stp x0, xzr, [sp, #-16]!
101 ldp x0, xzr, [sp], #16
124 ldr x1, [sp]
125 mov sp, x1
141 str x1, [sp, #-16]!
144 ldr x1, [sp], #16
/Zephyr-latest/arch/mips/core/
Disr.S40 op ra, ESF_O(ra)(sp) ;\
41 op gp, ESF_O(gp)(sp) ;\
42 op AT, ESF_O(at)(sp) ;\
43 op t0, ESF_O(t0)(sp) ;\
44 op t1, ESF_O(t1)(sp) ;\
45 op t2, ESF_O(t2)(sp) ;\
46 op t3, ESF_O(t3)(sp) ;\
47 op t4, ESF_O(t4)(sp) ;\
48 op t5, ESF_O(t5)(sp) ;\
49 op t6, ESF_O(t6)(sp) ;\
[all …]
/Zephyr-latest/arch/arm/core/cortex_a_r/
Dexc.S52 srsdb sp!, #\mode
53 stmfd sp, {r0-r3, r12, lr}^
54 sub sp, #24
57 sub sp, #___fpu_t_SIZEOF
64 mov r2, sp
74 sub sp, #___extra_esf_info_t_SIZEOF
76 str r0, [sp, #4]
77 str r0, [sp, #8]
79 sub r1, sp, #___callee_saved_t_SIZEOF
80 str r1, [sp]
[all …]
Dexc_exit.S33 sub sp, #8
47 str r0, [sp, #8]
48 str r1, [sp, #12]
59 ldr sp, [r0, #_thread_offset_to_sp_usr] /* sp_usr */
87 add r3, sp, #___fpu_sf_t_fpscr_OFFSET
94 mov r3, sp
105 add sp, sp, #___fpu_t_SIZEOF
165 add sp, sp, r3
190 rfeia sp!
229 add sp, sp, #___fpu_t_SIZEOF
[all …]
/Zephyr-latest/soc/intel/intel_adsp/common/include/
Ddebug_helpers.h25 static inline bool intel_adsp_ptr_is_sane(uint32_t sp) in intel_adsp_ptr_is_sane() argument
27 return ((char *)sp >= _end && (char *)sp <= _heap_sentry) || in intel_adsp_ptr_is_sane()
28 ((char *)sp >= _cached_start && (char *)sp <= _cached_end) || in intel_adsp_ptr_is_sane()
29 (sp >= (IMR_BOOT_LDR_MANIFEST_BASE - CONFIG_ISR_STACK_SIZE) in intel_adsp_ptr_is_sane()
30 && sp <= IMR_BOOT_LDR_MANIFEST_BASE); in intel_adsp_ptr_is_sane()
/Zephyr-latest/soc/nordic/common/vpr/
Dsoc_isr_stacking.h93 addi t1, sp, __struct_arch_esf_soc_context_OFFSET; \
94 lr t0, __struct_arch_esf_mepc_OFFSET(sp); \
99 addi t1, sp, __struct_arch_esf_soc_context_OFFSET; \
101 lr t1, __struct_arch_esf_mepc_OFFSET(sp); \
103 sr t2, __struct_arch_esf_mepc_OFFSET(sp)
114 addi sp, sp, -ESF_SW_EXC_SIZEOF; \
119 addi sp, sp, -ESF_SW_IRQ_SIZEOF; \
131 addi sp, sp, ESF_SW_EXC_SIZEOF; \
135 addi sp, sp, ESF_SW_IRQ_SIZEOF; \
/Zephyr-latest/soc/espressif/esp32c2/
Dsoc_irq.S14 addi sp, sp,-4
15 sw ra, 0x00(sp)
18 lw ra, 0x00(sp)
19 addi sp, sp, 4
/Zephyr-latest/soc/espressif/esp32c3/
Dsoc_irq.S14 addi sp, sp,-4
15 sw ra, 0x00(sp)
18 lw ra, 0x00(sp)
19 addi sp, sp, 4
/Zephyr-latest/arch/xtensa/core/
Dxtensa_backtrace.c41 static inline bool xtensa_stack_ptr_is_sane(uint32_t sp) in xtensa_stack_ptr_is_sane() argument
46 valid = esp_stack_ptr_is_sane(sp); in xtensa_stack_ptr_is_sane()
48 valid = intel_adsp_ptr_is_sane(sp); in xtensa_stack_ptr_is_sane()
58 valid = !xtensa_is_outside_stack_bounds(sp, 0, UINT32_MAX); in xtensa_stack_ptr_is_sane()
82 if (xtensa_is_outside_stack_bounds((uintptr_t)frame->sp, 0, UINT32_MAX)) { in xtensa_backtrace_get_next_frame()
91 char *base_save = (char *)frame->sp; in xtensa_backtrace_get_next_frame()
98 frame->sp = *((uint32_t *)(base_save - 12)); in xtensa_backtrace_get_next_frame()
103 return (xtensa_stack_ptr_is_sane(frame->sp) && in xtensa_backtrace_get_next_frame()
133 xtensa_backtrace_get_start(&(stk_frame.pc), &(stk_frame.sp), in xtensa_backtrace_print()
142 stk_frame.sp); in xtensa_backtrace_print()
[all …]
/Zephyr-latest/lib/os/
Dcbprintf_complete.c320 const char *sp = *str; in extract_decimal() local
323 while (isdigit((int)(unsigned char)*sp) != 0) { in extract_decimal()
324 val = 10U * val + *sp++ - '0'; in extract_decimal()
326 *str = sp; in extract_decimal()
340 const char *sp) in extract_flags() argument
345 switch (*sp) { in extract_flags()
365 ++sp; in extract_flags()
376 return sp; in extract_flags()
389 const char *sp) in extract_width() argument
393 if (*sp == '*') { in extract_width()
[all …]
/Zephyr-latest/soc/espressif/esp32c6/
Dsoc_irq.S20 addi sp, sp,-4
21 sw ra, 0x00(sp)
24 lw ra, 0x00(sp)
25 addi sp, sp, 4
/Zephyr-latest/arch/arc/core/
Duserspace.S70 mov_s blink, sp
105 mov_s sp, r5
112 mov r5, sp /* skip r0, r1, r2, r3 */
169 mov_s sp, blink
203 ld_s r0, [sp, ___isf_t_r0_OFFSET]
204 ld_s r1, [sp, ___isf_t_r1_OFFSET]
205 ld_s r2, [sp, ___isf_t_r2_OFFSET]
207 mov r7, sp
215 st_s r0, [sp, ___isf_t_r0_OFFSET]
227 ld_s r0, [sp, ___isf_t_sec_stat_OFFSET]
[all …]
Dfast_irq.S81 mov_s r0, sp
83 _get_curr_cpu_irq_stack sp
106 sr sp, [_ARC_V2_USER_SP]
111 add sp, sp, 8
117 lr sp, [_ARC_V2_USER_SP]
162 pop sp
175 pop sp
207 aex sp, [_ARC_V2_USER_SP]
211 aex sp, [_ARC_V2_USER_SP]
230 st_s r0, [sp, ___isf_t_status32_OFFSET]
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_nuclei_eclic.S37 addi sp, sp, -16
38 sw ra, 0(sp)
77 lw ra, 0(sp)
78 addi sp, sp, 16

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