Lines Matching refs:sp
26 SUBR sp, sp, ___callee_saved_stack_t_SIZEOF
29 STR r13, sp, ___callee_saved_stack_t_r13_OFFSET
30 STR r14, sp, ___callee_saved_stack_t_r14_OFFSET
31 STR r15, sp, ___callee_saved_stack_t_r15_OFFSET
32 STR r16, sp, ___callee_saved_stack_t_r16_OFFSET
33 STR r17, sp, ___callee_saved_stack_t_r17_OFFSET
34 STR r18, sp, ___callee_saved_stack_t_r18_OFFSET
35 STR r19, sp, ___callee_saved_stack_t_r19_OFFSET
36 STR r20, sp, ___callee_saved_stack_t_r20_OFFSET
37 STR r21, sp, ___callee_saved_stack_t_r21_OFFSET
38 STR r22, sp, ___callee_saved_stack_t_r22_OFFSET
39 STR r23, sp, ___callee_saved_stack_t_r23_OFFSET
40 STR r24, sp, ___callee_saved_stack_t_r24_OFFSET
41 STR r25, sp, ___callee_saved_stack_t_r25_OFFSET
42 STR r26, sp, ___callee_saved_stack_t_r26_OFFSET
43 STR fp, sp, ___callee_saved_stack_t_fp_OFFSET
49 st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
51 st_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
54 st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
56 st_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
60 st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
63 STR r30, sp, ___callee_saved_stack_t_r30_OFFSET
66 STR r58, sp, ___callee_saved_stack_t_r58_OFFSET
68 STR r59, sp, ___callee_saved_stack_t_r59_OFFSET
76 st_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
78 st_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
82 st_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
84 st_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
86 st_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
88 st_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
94 STR sp, r2, _thread_offset_to_sp
100 LDR sp, r2, _thread_offset_to_sp
103 LDR r58, sp, ___callee_saved_stack_t_r58_OFFSET
105 LDR r59, sp, ___callee_saved_stack_t_r59_OFFSET
113 ld_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
115 ld_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
119 ld_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
121 ld_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
123 ld_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
125 ld_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
134 ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
136 ld_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
139 ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
141 ld_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
145 ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
150 LDR r13, sp, ___callee_saved_stack_t_r13_OFFSET
151 LDR r14, sp, ___callee_saved_stack_t_r14_OFFSET
152 LDR r15, sp, ___callee_saved_stack_t_r15_OFFSET
153 LDR r16, sp, ___callee_saved_stack_t_r16_OFFSET
154 LDR r17, sp, ___callee_saved_stack_t_r17_OFFSET
155 LDR r18, sp, ___callee_saved_stack_t_r18_OFFSET
156 LDR r19, sp, ___callee_saved_stack_t_r19_OFFSET
157 LDR r20, sp, ___callee_saved_stack_t_r20_OFFSET
158 LDR r21, sp, ___callee_saved_stack_t_r21_OFFSET
159 LDR r22, sp, ___callee_saved_stack_t_r22_OFFSET
160 LDR r23, sp, ___callee_saved_stack_t_r23_OFFSET
161 LDR r24, sp, ___callee_saved_stack_t_r24_OFFSET
162 LDR r25, sp, ___callee_saved_stack_t_r25_OFFSET
163 LDR r26, sp, ___callee_saved_stack_t_r26_OFFSET
164 LDR fp, sp, ___callee_saved_stack_t_fp_OFFSET
165 LDR r30, sp, ___callee_saved_stack_t_r30_OFFSET
167 ADDR sp, sp, ___callee_saved_stack_t_SIZEOF
173 ADDR sp, sp, ___callee_saved_stack_t_SIZEOF
182 SUBR sp, sp, ___isf_t_SIZEOF
184 STR blink, sp, ___isf_t_blink_OFFSET
188 STR r13, sp, ___isf_t_r13_OFFSET
189 STR r12, sp, ___isf_t_r12_OFFSET
190 STR r11, sp, ___isf_t_r11_OFFSET
191 STR r10, sp, ___isf_t_r10_OFFSET
192 STR r9, sp, ___isf_t_r9_OFFSET
193 STR r8, sp, ___isf_t_r8_OFFSET
194 STR r7, sp, ___isf_t_r7_OFFSET
195 STR r6, sp, ___isf_t_r6_OFFSET
196 STR r5, sp, ___isf_t_r5_OFFSET
197 STR r4, sp, ___isf_t_r4_OFFSET
198 STR r3, sp, ___isf_t_r3_OFFSET
199 STR r2, sp, ___isf_t_r2_OFFSET
200 STR r1, sp, ___isf_t_r1_OFFSET
201 STR r0, sp, ___isf_t_r0_OFFSET
205 STR r0, sp, ___isf_t_lp_count_OFFSET
208 STR r1, sp, ___isf_t_lp_start_OFFSET
209 STR r0, sp, ___isf_t_lp_end_OFFSET
216 st_s r1, [sp, ___isf_t_jli_base_OFFSET]
217 st_s r0, [sp, ___isf_t_ldi_base_OFFSET]
218 st_s r2, [sp, ___isf_t_ei_base_OFFSET]
229 LDR blink, sp, ___isf_t_blink_OFFSET
232 ld_s r1, [sp, ___isf_t_jli_base_OFFSET]
233 ld_s r0, [sp, ___isf_t_ldi_base_OFFSET]
234 ld_s r2, [sp, ___isf_t_ei_base_OFFSET]
241 LDR r0, sp, ___isf_t_lp_count_OFFSET
243 LDR r1, sp, ___isf_t_lp_start_OFFSET
244 LDR r0, sp, ___isf_t_lp_end_OFFSET
249 LDR r13, sp, ___isf_t_r13_OFFSET
250 LDR r12, sp, ___isf_t_r12_OFFSET
251 LDR r11, sp, ___isf_t_r11_OFFSET
252 LDR r10, sp, ___isf_t_r10_OFFSET
253 LDR r9, sp, ___isf_t_r9_OFFSET
254 LDR r8, sp, ___isf_t_r8_OFFSET
255 LDR r7, sp, ___isf_t_r7_OFFSET
256 LDR r6, sp, ___isf_t_r6_OFFSET
257 LDR r5, sp, ___isf_t_r5_OFFSET
258 LDR r4, sp, ___isf_t_r4_OFFSET
259 LDR r3, sp, ___isf_t_r3_OFFSET
260 LDR r2, sp, ___isf_t_r2_OFFSET
261 LDR r1, sp, ___isf_t_r1_OFFSET
262 LDR r0, sp, ___isf_t_r0_OFFSET
274 ADDR sp, sp, ___isf_t_SIZEOF
506 MOVR r0, sp