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Searched refs:XCHAL_MPU_BACKGROUND_ENTRIES (Results 1 – 13 of 13) sorted by relevance

/hal_xtensa-latest/src/hal/
Dmpu.c131 for (i = 0; i < XCHAL_MPU_BACKGROUND_ENTRIES; i++) in assert_maps_equivalent()
379 for (i = XCHAL_MPU_BACKGROUND_ENTRIES - 1; i >= 0; i--) in _xthal_get_entry()
395 for (i = 0; i < XCHAL_MPU_BACKGROUND_ENTRIES; i++) in _xthal_in_bgmap()
628 for (i = XCHAL_MPU_BACKGROUND_ENTRIES - 1; i >= 0; i--) in get_bg_map_index()
825 for (i = XCHAL_MPU_BACKGROUND_ENTRIES - 1; i >= 0; i--) in handle_invalid_pred()
958 …for (next_bg_entry_index = 0; next_bg_entry_index < XCHAL_MPU_BACKGROUND_ENTRIES; next_bg_entry_in… in create_aligning_entries_if_required()
1003 for (i = XCHAL_MPU_BACKGROUND_ENTRIES - 1; i >= 0; i--) in start_initial_region()
1578 for (i = XCHAL_MPU_BACKGROUND_ENTRIES - 1; i > 0; i--) in xthal_get_entry_for_address()
1738 int bg_index = XCHAL_MPU_BACKGROUND_ENTRIES - 1; in xthal_calc_cacheadrdis()
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h598 #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h598 #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h598 #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h621 #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h634 #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h692 #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h692 #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h715 #define XCHAL_MPU_BACKGROUND_ENTRIES 2 /* number of entries in bg map*/ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h663 #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h729 #define XCHAL_MPU_BACKGROUND_ENTRIES 2 /* number of entries in bg map*/ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h787 #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h802 #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ macro