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Searched refs:XSHAL_TRAPNULL_CACHEATTR_WRITEBACK (Results 1 – 7 of 7) sorted by relevance

/hal_xtensa-2.7.6/zephyr/soc/nxp_imx8/xtensa/config/
Dsystem.h183 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2224242F /* enable caches in write-back mode */ macro
187 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
194 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
198 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-2.7.6/zephyr/soc/sample_controller/xtensa/config/
Dsystem.h183 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */ macro
187 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
194 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
198 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-2.7.6/zephyr/soc/intel_s1000/xtensa/config/
Dsystem.h172 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */ macro
176 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
183 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
187 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-2.7.6/zephyr/soc/intel_apl_adsp/xtensa/config/
Dsystem.h187 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */ macro
191 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
198 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_18/xtensa/config/
Dsystem.h187 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */ macro
191 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
198 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_25/xtensa/config/
Dsystem.h187 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */ macro
191 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
198 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_20/xtensa/config/
Dsystem.h187 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */ macro
191 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
198 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK