Home
last modified time | relevance | path

Searched refs:GPT_O_CTL (Results 1 – 6 of 6) sorted by relevance

/hal_ti-3.4.0/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/
Dtimer.c143 HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); in TimerConfigure()
170 HWREG(ui32Base + GPT_O_CTL) = (bInvert ? in TimerLevelControl()
171 (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : in TimerLevelControl()
172 (HWREG(ui32Base + GPT_O_CTL) & in TimerLevelControl()
191 HWREG(ui32Base + GPT_O_CTL) = (bStall ? in TimerStallControl()
192 (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : in TimerStallControl()
193 (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); in TimerStallControl()
Dtimer.h243 HWREG(ui32Base + GPT_O_CTL) |= ui32Timer & (GPT_CTL_TAEN | GPT_CTL_TBEN); in TimerEnable()
270 HWREG(ui32Base + GPT_O_CTL) &= ~(ui32Timer & in TimerDisable()
379 HWREG(ui32Base + GPT_O_CTL) = ((HWREG(ui32Base + GPT_O_CTL) & ~ui32Timer) | in TimerEventControl()
/hal_ti-3.4.0/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/
Dtimer.c141 HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); in TimerConfigure()
168 HWREG(ui32Base + GPT_O_CTL) = (bInvert ? in TimerLevelControl()
169 (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : in TimerLevelControl()
170 (HWREG(ui32Base + GPT_O_CTL) & in TimerLevelControl()
189 HWREG(ui32Base + GPT_O_CTL) = (bStall ? in TimerStallControl()
190 (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : in TimerStallControl()
191 (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); in TimerStallControl()
Dtimer.h241 HWREG(ui32Base + GPT_O_CTL) |= ui32Timer & (GPT_CTL_TAEN | GPT_CTL_TBEN); in TimerEnable()
268 HWREG(ui32Base + GPT_O_CTL) &= ~(ui32Timer & in TimerDisable()
377 HWREG(ui32Base + GPT_O_CTL) = ((HWREG(ui32Base + GPT_O_CTL) & ~ui32Timer) | in TimerEventControl()
/hal_ti-3.4.0/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/inc/
Dhw_gpt.h56 #define GPT_O_CTL 0x0000000C macro
/hal_ti-3.4.0/simplelink/source/ti/devices/cc13x2_cc26x2/inc/
Dhw_gpt.h56 #define GPT_O_CTL 0x0000000C macro