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Searched refs:COMP_CSR_BLANKING_Pos (Results 1 – 25 of 56) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g051xx.h7497 #define COMP_CSR_BLANKING_Pos (20U) macro
7498 #define COMP_CSR_BLANKING_Msk (0x1FUL << COMP_CSR_BLANKING_Pos) /*!< 0x01F00000 */
7500 #define COMP_CSR_BLANKING_0 (0x01UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
7501 #define COMP_CSR_BLANKING_1 (0x02UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
7502 #define COMP_CSR_BLANKING_2 (0x04UL << COMP_CSR_BLANKING_Pos) /*!< 0x00400000 */
7503 #define COMP_CSR_BLANKING_3 (0x08UL << COMP_CSR_BLANKING_Pos) /*!< 0x00800000 */
7504 #define COMP_CSR_BLANKING_4 (0x10UL << COMP_CSR_BLANKING_Pos) /*!< 0x01000000 */
Dstm32g061xx.h7801 #define COMP_CSR_BLANKING_Pos (20U) macro
7802 #define COMP_CSR_BLANKING_Msk (0x1FUL << COMP_CSR_BLANKING_Pos) /*!< 0x01F00000 */
7804 #define COMP_CSR_BLANKING_0 (0x01UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
7805 #define COMP_CSR_BLANKING_1 (0x02UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
7806 #define COMP_CSR_BLANKING_2 (0x04UL << COMP_CSR_BLANKING_Pos) /*!< 0x00400000 */
7807 #define COMP_CSR_BLANKING_3 (0x08UL << COMP_CSR_BLANKING_Pos) /*!< 0x00800000 */
7808 #define COMP_CSR_BLANKING_4 (0x10UL << COMP_CSR_BLANKING_Pos) /*!< 0x01000000 */
Dstm32g071xx.h7881 #define COMP_CSR_BLANKING_Pos (20U) macro
7882 #define COMP_CSR_BLANKING_Msk (0x1FUL << COMP_CSR_BLANKING_Pos) /*!< 0x01F00000 */
7884 #define COMP_CSR_BLANKING_0 (0x01UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
7885 #define COMP_CSR_BLANKING_1 (0x02UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
7886 #define COMP_CSR_BLANKING_2 (0x04UL << COMP_CSR_BLANKING_Pos) /*!< 0x00400000 */
7887 #define COMP_CSR_BLANKING_3 (0x08UL << COMP_CSR_BLANKING_Pos) /*!< 0x00800000 */
7888 #define COMP_CSR_BLANKING_4 (0x10UL << COMP_CSR_BLANKING_Pos) /*!< 0x01000000 */
Dstm32g081xx.h8185 #define COMP_CSR_BLANKING_Pos (20U) macro
8186 #define COMP_CSR_BLANKING_Msk (0x1FUL << COMP_CSR_BLANKING_Pos) /*!< 0x01F00000 */
8188 #define COMP_CSR_BLANKING_0 (0x01UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
8189 #define COMP_CSR_BLANKING_1 (0x02UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
8190 #define COMP_CSR_BLANKING_2 (0x04UL << COMP_CSR_BLANKING_Pos) /*!< 0x00400000 */
8191 #define COMP_CSR_BLANKING_3 (0x08UL << COMP_CSR_BLANKING_Pos) /*!< 0x00800000 */
8192 #define COMP_CSR_BLANKING_4 (0x10UL << COMP_CSR_BLANKING_Pos) /*!< 0x01000000 */
Dstm32g0c1xx.h9769 #define COMP_CSR_BLANKING_Pos (20U) macro
9770 #define COMP_CSR_BLANKING_Msk (0x1FUL << COMP_CSR_BLANKING_Pos) /*!< 0x01F00000 */
9772 #define COMP_CSR_BLANKING_0 (0x01UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
9773 #define COMP_CSR_BLANKING_1 (0x02UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
9774 #define COMP_CSR_BLANKING_2 (0x04UL << COMP_CSR_BLANKING_Pos) /*!< 0x00400000 */
9775 #define COMP_CSR_BLANKING_3 (0x08UL << COMP_CSR_BLANKING_Pos) /*!< 0x00800000 */
9776 #define COMP_CSR_BLANKING_4 (0x10UL << COMP_CSR_BLANKING_Pos) /*!< 0x01000000 */
Dstm32g0b1xx.h9465 #define COMP_CSR_BLANKING_Pos (20U) macro
9466 #define COMP_CSR_BLANKING_Msk (0x1FUL << COMP_CSR_BLANKING_Pos) /*!< 0x01F00000 */
9468 #define COMP_CSR_BLANKING_0 (0x01UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
9469 #define COMP_CSR_BLANKING_1 (0x02UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
9470 #define COMP_CSR_BLANKING_2 (0x04UL << COMP_CSR_BLANKING_Pos) /*!< 0x00400000 */
9471 #define COMP_CSR_BLANKING_3 (0x08UL << COMP_CSR_BLANKING_Pos) /*!< 0x00800000 */
9472 #define COMP_CSR_BLANKING_4 (0x10UL << COMP_CSR_BLANKING_Pos) /*!< 0x01000000 */
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h1750 #define COMP_CSR_BLANKING_Pos (18U) macro
1751 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
1753 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
1754 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
1755 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
Dstm32wle5xx.h1750 #define COMP_CSR_BLANKING_Pos (18U) macro
1751 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
1753 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
1754 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
1755 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
Dstm32wl5mxx.h1932 #define COMP_CSR_BLANKING_Pos (18U) macro
1933 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
1935 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
1936 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
1937 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
Dstm32wl54xx.h1932 #define COMP_CSR_BLANKING_Pos (18U) macro
1933 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
1935 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
1936 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
1937 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
Dstm32wl55xx.h1932 #define COMP_CSR_BLANKING_Pos (18U) macro
1933 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
1935 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
1936 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
1937 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h1598 #define COMP_CSR_BLANKING_Pos (18U) macro
1599 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
1601 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
1602 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
1603 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
Dstm32wb35xx.h2244 #define COMP_CSR_BLANKING_Pos (18U) macro
2245 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
2247 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
2248 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2249 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
Dstm32wb55xx.h2290 #define COMP_CSR_BLANKING_Pos (18U) macro
2291 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
2293 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
2294 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2295 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
Dstm32wb5mxx.h2290 #define COMP_CSR_BLANKING_Pos (18U) macro
2291 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
2293 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
2294 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2295 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb15xx.h1598 #define COMP_CSR_BLANKING_Pos (18U) macro
1599 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
1601 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
1602 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
1603 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h2105 #define COMP_CSR_BLANKING_Pos (19U) macro
2106 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
2108 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2109 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
2110 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
Dstm32g411xc.h2142 #define COMP_CSR_BLANKING_Pos (19U) macro
2143 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
2145 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2146 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
2147 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
Dstm32g441xx.h2450 #define COMP_CSR_BLANKING_Pos (19U) macro
2451 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
2453 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2454 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
2455 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
Dstm32gbk1cb.h2215 #define COMP_CSR_BLANKING_Pos (19U) macro
2216 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
2218 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2219 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
2220 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
Dstm32g431xx.h2229 #define COMP_CSR_BLANKING_Pos (19U) macro
2230 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
2232 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2233 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
2234 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
Dstm32g4a1xx.h2530 #define COMP_CSR_BLANKING_Pos (19U) macro
2531 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
2533 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2534 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
2535 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
Dstm32g491xx.h2309 #define COMP_CSR_BLANKING_Pos (19U) macro
2310 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
2312 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2313 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
2314 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h9083 #define COMP_CSR_BLANKING_Pos (18U) macro
9084 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
9086 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
9087 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
9088 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
Dstm32l412xx.h8858 #define COMP_CSR_BLANKING_Pos (18U) macro
8859 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
8861 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
8862 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
8863 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */

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