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Searched refs:INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1 (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h35208 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_R… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h35178 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_R… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h45399 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_R… macro
DMCXN546_cm33_core1.h45399 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_R… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h45399 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_R… macro
DMCXN547_cm33_core1.h45399 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_R… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h45826 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_R… macro
DMCXN947_cm33_core0.h45826 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_R… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h45826 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_R… macro
DMCXN946_cm33_core1.h45826 #define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_R… macro