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Searched refs:DividerIndex (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.7.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Divider.c141 uint32 DividerIndex; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() local
157 DividerIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_DIVIDER_INDEX]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
160 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
169 if((Instance == 0U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
173 else if((Instance == 4U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
191 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
212 (void)DividerIndex; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
230 uint32 DividerIndex; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger() local
246 DividerIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_DIVIDER_INDEX]; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
249 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
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DClock_Ip_FracDiv.c139 uint32 DividerIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_DIVIDER_INDEX]; in Clock_Ip_ResetDfsMfiMfn() local
142 Clock_Ip_apxDfs[Instance]->PORTRESET |= (1UL << DividerIndex); in Clock_Ip_ResetDfsMfiMfn()
148 uint32 DividerIndex; in Clock_Ip_SetDfsMfiMfn() local
157 DividerIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_DIVIDER_INDEX]; in Clock_Ip_SetDfsMfiMfn()
167 Clock_Ip_apxDfs[Instance]->DVPORT[DividerIndex] = Value; in Clock_Ip_SetDfsMfiMfn()
170 Clock_Ip_apxDfs[Instance]->PORTRESET &= ~(1UL << DividerIndex); in Clock_Ip_SetDfsMfiMfn()
185 uint32 DividerIndex = Clock_Ip_au8ClockFeatures[DfsName][CLOCK_IP_DIVIDER_INDEX]; in Clock_Ip_CompleteDfsMfiMfn() local
188 if (0U == (Clock_Ip_apxDfs[Instance]->PORTRESET & (1UL << DividerIndex))) in Clock_Ip_CompleteDfsMfiMfn()
194 …stance]->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & (1UL << DividerIndex)); in Clock_Ip_CompleteDfsMfiMfn()
DClock_Ip_Pll.c171 uint8 DividerIndex; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize() local
178 for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++) in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
180 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
189 (void)DividerIndex; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
315 uint8 DividerIndex; in Clock_Ip_ResetPlldigRdivMfiMfnSdmen() local
322 for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++) in Clock_Ip_ResetPlldigRdivMfiMfnSdmen()
324 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmen()
333 (void)DividerIndex; in Clock_Ip_ResetPlldigRdivMfiMfnSdmen()
/hal_nxp-3.7.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Divider.c140 uint32 DividerIndex; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() local
156 DividerIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_DIVIDER_INDEX]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
163 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
166 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
169 if((Instance == 0U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
173 else if((Instance == 4U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
199 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] |= MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
203 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
216 (void)DividerIndex; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
233 uint32 DividerIndex; in Clock_Ip_SetPllPll0divDeDivOutput() local
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DClock_Ip_Pll.c164 uint8 DividerIndex; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize() local
171 for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++) in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
173 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLL_PLLODIV_DE_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
181 (void)DividerIndex; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
301 uint8 DividerIndex; in Clock_Ip_ResetPllRdivMfiMfnOdiv2Sdmen() local
308 for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++) in Clock_Ip_ResetPllRdivMfiMfnOdiv2Sdmen()
310 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLL_PLLODIV_DE_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2Sdmen()
318 (void)DividerIndex; in Clock_Ip_ResetPllRdivMfiMfnOdiv2Sdmen()