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Searched refs:refDiv (Results 1 – 23 of 23) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmimx8mq/
Dclock_config.c41 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
50 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
59 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/project_template/
Dclock_config.c28 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
37 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
46 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/project_template/
Dclock_config.c28 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
37 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
46 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/project_template/
Dclock_config.c28 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
37 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
46 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/project_template/
Dclock_config.c28 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
37 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
46 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/project_template/
Dclock_config.c28 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
37 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
46 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmimx8mq/project_template/
Dclock_config.c30 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
39 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
48 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/
Dsystem_MIMX8MQ5_cm4.c81 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_… in GetFracPllFreq() local
104 refClkFreq /= (uint32_t)refDiv + 1U; in GetFracPllFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/
Dsystem_MIMX8MQ6_cm4.c81 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_… in GetFracPllFreq() local
104 refClkFreq /= (uint32_t)refDiv + 1U; in GetFracPllFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/
Dsystem_MIMX8MQ7_cm4.c81 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_… in GetFracPllFreq() local
104 refClkFreq /= (uint32_t)refDiv + 1U; in GetFracPllFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/
Dsystem_MIMX8MD6_cm4.c81 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_… in GetFracPllFreq() local
104 refClkFreq /= (uint32_t)refDiv + 1U; in GetFracPllFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/
Dsystem_MIMX8MD7_cm4.c81 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_… in GetFracPllFreq() local
104 refClkFreq /= (uint32_t)refDiv + 1U; in GetFracPllFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/drivers/
Dfsl_clock.c783 assert((config->refDiv != 0U) && (config->outDiv != 0U)); in CLOCK_InitFracPll()
798 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL((uint32_t)(config->refDiv) - 1U)) | in CLOCK_InitFracPll()
836 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFC… in CLOCK_GetFracPllFreq() local
845 refClkFreq /= (uint32_t)refDiv + 1UL; in CLOCK_GetFracPllFreq()
Dfsl_clock.h984 … uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/drivers/
Dfsl_clock.c783 assert((config->refDiv != 0U) && (config->outDiv != 0U)); in CLOCK_InitFracPll()
798 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL((uint32_t)(config->refDiv) - 1U)) | in CLOCK_InitFracPll()
836 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFC… in CLOCK_GetFracPllFreq() local
845 refClkFreq /= (uint32_t)refDiv + 1UL; in CLOCK_GetFracPllFreq()
Dfsl_clock.h984 … uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/drivers/
Dfsl_clock.c783 assert((config->refDiv != 0U) && (config->outDiv != 0U)); in CLOCK_InitFracPll()
798 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL((uint32_t)(config->refDiv) - 1U)) | in CLOCK_InitFracPll()
836 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFC… in CLOCK_GetFracPllFreq() local
845 refClkFreq /= (uint32_t)refDiv + 1UL; in CLOCK_GetFracPllFreq()
Dfsl_clock.h984 … uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/drivers/
Dfsl_clock.c783 assert((config->refDiv != 0U) && (config->outDiv != 0U)); in CLOCK_InitFracPll()
798 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL((uint32_t)(config->refDiv) - 1U)) | in CLOCK_InitFracPll()
836 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFC… in CLOCK_GetFracPllFreq() local
845 refClkFreq /= (uint32_t)refDiv + 1UL; in CLOCK_GetFracPllFreq()
Dfsl_clock.h984 … uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/drivers/
Dfsl_clock.c783 assert((config->refDiv != 0U) && (config->outDiv != 0U)); in CLOCK_InitFracPll()
798 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL((uint32_t)(config->refDiv) - 1U)) | in CLOCK_InitFracPll()
836 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFC… in CLOCK_GetFracPllFreq() local
845 refClkFreq /= (uint32_t)refDiv + 1UL; in CLOCK_GetFracPllFreq()
Dfsl_clock.h984 … uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/components/codec/wm8962/
Dfsl_wm8962.c143 uint16_t refDiv = 0U, fllLock = 0U; in WM8962_SetInternalFllConfig() local
149 …(WM8962_GetClockDivider(fllConfig->fllReferenceClockFreq, WM8962_FLL_MAX_REFERENCE_CLOCK, &refDiv), in WM8962_SetInternalFllConfig()
152 refClock = fllConfig->fllReferenceClockFreq / (uint32_t)(1UL << (refDiv & 3U)); in WM8962_SetInternalFllConfig()
221 …WM8962_CHECK_RET(WM8962_ModifyReg(handle, WM8962_FLL_CTRL_2, 0x1FBU, (uint16_t)(refDiv | (fllOutDi… in WM8962_SetInternalFllConfig()