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Searched refs:lateConfig (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1175/drivers/cm7/
Dfsl_cache.c210 if (config->lateConfig) in L2CACHE_Init()
214 data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
215 L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
216 L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | in L2CACHE_Init()
217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
220 data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
221 L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
222 L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
261 config->lateConfig = NULL; in L2CACHE_GetDefaultConfig()
Dfsl_cache.h104 …L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1176/drivers/cm7/
Dfsl_cache.c210 if (config->lateConfig) in L2CACHE_Init()
214 data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
215 L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
216 L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | in L2CACHE_Init()
217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
220 data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
221 L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
222 L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
261 config->lateConfig = NULL; in L2CACHE_GetDefaultConfig()
Dfsl_cache.h104 …L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML6/drivers/
Dfsl_cache.c210 if (config->lateConfig) in L2CACHE_Init()
214 data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
215 L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
216 L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | in L2CACHE_Init()
217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
220 data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
221 L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
222 L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
261 config->lateConfig = NULL; in L2CACHE_GetDefaultConfig()
Dfsl_cache.h104 …L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1173/drivers/cm7/
Dfsl_cache.c210 if (config->lateConfig) in L2CACHE_Init()
214 data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
215 L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
216 L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | in L2CACHE_Init()
217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
220 data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
221 L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
222 L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
261 config->lateConfig = NULL; in L2CACHE_GetDefaultConfig()
Dfsl_cache.h104 …L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/cache/armv7-m7/
Dfsl_cache.c210 if (config->lateConfig) in L2CACHE_Init()
214 data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
215 L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
216 L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | in L2CACHE_Init()
217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
220 data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
221 L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
222 L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
261 config->lateConfig = NULL; in L2CACHE_GetDefaultConfig()
Dfsl_cache.h104 …L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1166/drivers/cm7/
Dfsl_cache.c210 if (config->lateConfig) in L2CACHE_Init()
214 data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
215 L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
216 L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | in L2CACHE_Init()
217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
220 data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
221 L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
222 L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
261 config->lateConfig = NULL; in L2CACHE_GetDefaultConfig()
Dfsl_cache.h104 …L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1165/drivers/cm7/
Dfsl_cache.c210 if (config->lateConfig) in L2CACHE_Init()
214 data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
215 L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
216 L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | in L2CACHE_Init()
217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
220 data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
221 L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
222 L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
261 config->lateConfig = NULL; in L2CACHE_GetDefaultConfig()
Dfsl_cache.h104 …L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1171/drivers/cm7/
Dfsl_cache.c210 if (config->lateConfig) in L2CACHE_Init()
214 data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
215 L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
216 L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | in L2CACHE_Init()
217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
220 data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
221 L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
222 L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
261 config->lateConfig = NULL; in L2CACHE_GetDefaultConfig()
Dfsl_cache.h104 …L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1172/drivers/cm7/
Dfsl_cache.c210 if (config->lateConfig) in L2CACHE_Init()
214 data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
215 L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
216 L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | in L2CACHE_Init()
217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
220 data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
221 L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
222 L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
261 config->lateConfig = NULL; in L2CACHE_GetDefaultConfig()
Dfsl_cache.h104 …L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML4/drivers/
Dfsl_cache.c210 if (config->lateConfig) in L2CACHE_Init()
214 data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
215 L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
216 L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | in L2CACHE_Init()
217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
220 data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
221 L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
222 L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
261 config->lateConfig = NULL; in L2CACHE_GetDefaultConfig()
Dfsl_cache.h104 …L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML3/drivers/
Dfsl_cache.c210 if (config->lateConfig) in L2CACHE_Init()
214 data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
215 L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | in L2CACHE_Init()
216 L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | in L2CACHE_Init()
217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
220 data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
221 L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | in L2CACHE_Init()
222 L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
261 config->lateConfig = NULL; in L2CACHE_GetDefaultConfig()
Dfsl_cache.h104 …L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ member