| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1175/drivers/cm7/ |
| D | fsl_cache.c | 217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
|
| D | fsl_cache.h | 91 l2cache_latency_t dataWriteLate; /*!< Data write latency. */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1176/drivers/cm7/ |
| D | fsl_cache.c | 217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
|
| D | fsl_cache.h | 91 l2cache_latency_t dataWriteLate; /*!< Data write latency. */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML6/drivers/ |
| D | fsl_cache.c | 217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
|
| D | fsl_cache.h | 91 l2cache_latency_t dataWriteLate; /*!< Data write latency. */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1173/drivers/cm7/ |
| D | fsl_cache.c | 217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
|
| D | fsl_cache.h | 91 l2cache_latency_t dataWriteLate; /*!< Data write latency. */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/drivers/cache/armv7-m7/ |
| D | fsl_cache.c | 217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
|
| D | fsl_cache.h | 91 l2cache_latency_t dataWriteLate; /*!< Data write latency. */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1166/drivers/cm7/ |
| D | fsl_cache.c | 217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
|
| D | fsl_cache.h | 91 l2cache_latency_t dataWriteLate; /*!< Data write latency. */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1165/drivers/cm7/ |
| D | fsl_cache.c | 217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
|
| D | fsl_cache.h | 91 l2cache_latency_t dataWriteLate; /*!< Data write latency. */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1171/drivers/cm7/ |
| D | fsl_cache.c | 217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
|
| D | fsl_cache.h | 91 l2cache_latency_t dataWriteLate; /*!< Data write latency. */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1172/drivers/cm7/ |
| D | fsl_cache.c | 217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
|
| D | fsl_cache.h | 91 l2cache_latency_t dataWriteLate; /*!< Data write latency. */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML4/drivers/ |
| D | fsl_cache.c | 217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
|
| D | fsl_cache.h | 91 l2cache_latency_t dataWriteLate; /*!< Data write latency. */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML3/drivers/ |
| D | fsl_cache.c | 217 L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
223 L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); in L2CACHE_Init()
|
| D | fsl_cache.h | 91 l2cache_latency_t dataWriteLate; /*!< Data write latency. */ member
|
