CLOCK_IP_HAS_EDMA0_TCD28_CLK (reference) in projects: hal_nxp-3.5.0

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Searched refs:CLOCK_IP_HAS_EDMA0_TCD28_CLK (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.5.0/s32/soc/s32k344/include/
D	Clock_Ip_Cfg_Defines.h	`281 #define CLOCK_IP_HAS_EDMA0_TCD28_CLK 64U macro`
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/include/
D	Clock_Ip_Types.h	`1253 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 1254 EDMA0_TCD28_CLK = CLOCK_IP_HAS_EDMA0_TCD28_CLK,`
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/include/
D	Clock_Ip_Types.h	`1304 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 1305 EDMA0_TCD28_CLK = CLOCK_IP_HAS_EDMA0_TCD28_CLK,`
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
D	Clock_Ip_Frequency.c	`326 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 1154 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 2466 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK)`
D	Clock_Ip_Data.c	`293 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 1240 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 1953 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 2819 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 3936 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK)`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
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cmsis-3.5.0
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cmsis-nn-3.6.0-3.5.0
cmsis-nn-3.7.0
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edtt-3.7.0
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