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Searched refs:C2 (Results 1 – 25 of 81) sorted by relevance

1234

/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_uart.c272 base->C2 &= ~((uint8_t)UART_C2_TE_MASK | (uint8_t)UART_C2_RE_MASK); in UART_Init()
334 temp = base->C2; in UART_Init()
346 base->C2 = temp; in UART_Init()
372 base->C2 = 0; in UART_Deinit()
480 oldCtrl = base->C2; in UART_SetBaudRate()
483 base->C2 &= ~((uint8_t)UART_C2_TE_MASK | (uint8_t)UART_C2_RE_MASK); in UART_SetBaudRate()
494 base->C2 = oldCtrl; in UART_SetBaudRate()
573 base->C2 |= (uint8_t)(mask >> 8); in UART_EnableInterrupts()
601 base->C2 &= ~(uint8_t)(mask >> 8); in UART_DisableInterrupts()
634 temp |= ((uint32_t)(base->C2) << 8); in UART_GetEnabledInterrupts()
[all …]
Dfsl_acmp.c421 base->C2 &= ~(tmp32); in ACMP_SetRoundRobinConfig()
435 tmp32 = (base->C2 & in ACMP_SetRoundRobinConfig()
442 base->C2 = tmp32; in ACMP_SetRoundRobinConfig()
459 uint32_t tmp32 = (base->C2 & ~(CMP_C2_ACOn_MASK | CMP_C2_CHnF_MASK)); in ACMP_SetRoundRobinPreState()
462 base->C2 = tmp32; in ACMP_SetRoundRobinPreState()
474 uint32_t tmp32 = (base->C2 & (~CMP_C2_CHnF_MASK)); in ACMP_ClearRoundRobinStatusFlags()
477 base->C2 = tmp32; in ACMP_ClearRoundRobinStatusFlags()
510 tmp32 = base->C2; in ACMP_EnableInterrupts()
513 base->C2 = tmp32; in ACMP_EnableInterrupts()
547 tmp32 = base->C2; in ACMP_DisableInterrupts()
[all …]
Dfsl_lpsci.h414 base->C2 |= UART0_C2_TIE_MASK; in LPSCI_EnableTxDMA()
419 base->C2 &= ~UART0_C2_TIE_MASK; in LPSCI_EnableTxDMA()
436 base->C2 |= UART0_C2_RIE_MASK; in LPSCI_EnableRxDMA()
441 base->C2 &= ~UART0_C2_RIE_MASK; in LPSCI_EnableRxDMA()
465 base->C2 |= UART0_C2_TE_MASK; in LPSCI_EnableTx()
469 base->C2 &= ~UART0_C2_TE_MASK; in LPSCI_EnableTx()
485 base->C2 |= UART0_C2_RE_MASK; in LPSCI_EnableRx()
489 base->C2 &= ~UART0_C2_RE_MASK; in LPSCI_EnableRx()
Dfsl_spi.c159 bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; in SPI_WriteNonBlocking()
168 if (base->C2 & SPI_C2_SPIMODE_MASK) in SPI_WriteNonBlocking()
198 bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; in SPI_ReadNonBlocking()
207 if (base->C2 & SPI_C2_SPIMODE_MASK) in SPI_ReadNonBlocking()
426 base->C2 = SPI_C2_MODFEN(config->outputMode >> 1U) | SPI_C2_BIDIROE(config->pinMode >> 1U) | in SPI_MasterInit()
430 base->C2 = SPI_C2_MODFEN(config->outputMode >> 1U) | SPI_C2_BIDIROE(config->pinMode >> 1U) | in SPI_MasterInit()
489 base->C2 = SPI_C2_SPIMODE(config->dataMode) | SPI_C2_SPISWAI(config->enableStopInWaitMode); in SPI_SlaveInit()
491 base->C2 = SPI_C2_SPISWAI(config->enableStopInWaitMode); in SPI_SlaveInit()
554 base->C2 |= SPI_C2_SPMIE_MASK; in SPI_EnableInterrupts()
593 base->C2 &= (~SPI_C2_SPMIE_MASK); in SPI_DisableInterrupts()
[all …]
Dfsl_lpsci.c275 base->C2 &= ~(UART0_C2_TE_MASK | UART0_C2_RE_MASK); in LPSCI_Init()
309 temp = base->C2; in LPSCI_Init()
321 base->C2 = temp; in LPSCI_Init()
399 oldCtrl = base->C2; in LPSCI_SetBaudRate()
402 base->C2 &= ~(UART0_C2_TE_MASK | UART0_C2_RE_MASK); in LPSCI_SetBaudRate()
420 base->C2 = oldCtrl; in LPSCI_SetBaudRate()
438 base->C2 |= (mask >> 8); in LPSCI_EnableInterrupts()
449 base->C2 &= ~(mask >> 8); in LPSCI_DisableInterrupts()
456 temp = base->BDH | ((uint32_t)(base->C2) << 8) | ((uint32_t)(base->C3) << 16); in LPSCI_GetEnabledInterrupts()
913 if ((UART0_S1_RDRF_MASK & base->S1) && (UART0_C2_RIE_MASK & base->C2)) in LPSCI_TransferHandleIRQ()
[all …]
Dfsl_uart.h553 base->C2 |= (uint8_t)UART_C2_TIE_MASK; in UART_EnableTxDMA()
562 base->C2 &= ~(uint8_t)UART_C2_TIE_MASK; in UART_EnableTxDMA()
583 base->C2 |= (uint8_t)UART_C2_RIE_MASK; in UART_EnableRxDMA()
592 base->C2 &= ~(uint8_t)UART_C2_RIE_MASK; in UART_EnableRxDMA()
616 base->C2 |= (uint8_t)UART_C2_TE_MASK; in UART_EnableTx()
620 base->C2 &= ~(uint8_t)UART_C2_TE_MASK; in UART_EnableTx()
636 base->C2 |= (uint8_t)UART_C2_RE_MASK; in UART_EnableRx()
640 base->C2 &= ~(uint8_t)UART_C2_RE_MASK; in UART_EnableRx()
Dfsl_dac.c169 tmp8 = base->C2 & (uint8_t)(~DAC_C2_DACBFUP_MASK); in DAC_SetBufferConfig()
171 base->C2 = tmp8; in DAC_SetBufferConfig()
232 uint8_t tmp8 = base->C2 & (uint8_t)(~DAC_C2_DACBFRP_MASK); in DAC_SetBufferReadPointer()
235 base->C2 = tmp8; in DAC_SetBufferReadPointer()
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
Dfsl_clock.c100 #define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
101 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
512 if ((MCG->C2 & MCG_C2_LP_MASK) in CLOCK_GetFllFreq()
619 MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
629 MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); in CLOCK_SetInternalRefClkConfig()
658 MCG->C2 &= ~MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
662 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
714 MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
728 MCG->C2 &= ~OSC_MODE_MASK; in CLOCK_DeinitOsc0()
993 if (MCG->C2 & MCG_C2_EREFS_MASK) in CLOCK_SetFeeMode()
[all …]
Dsystem_MKW41Z4.c111 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
161 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dfsl_clock.c72 #define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
73 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
537 if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) in CLOCK_GetFllFreq()
637 MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
647 MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); in CLOCK_SetInternalRefClkConfig()
791 MCG->C2 &= ~MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
795 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
872 MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
886 MCG->C2 &= ~OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1160 if (MCG->C2 & MCG_C2_EREFS_MASK) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dfsl_clock.c72 #define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
73 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
561 if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) in CLOCK_GetFllFreq()
690 MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
700 MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); in CLOCK_SetInternalRefClkConfig()
844 MCG->C2 &= ~MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
848 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
955 MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
969 MCG->C2 &= ~OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1244 if (MCG->C2 & MCG_C2_EREFS_MASK) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dfsl_clock.c72 #define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
73 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
561 if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) in CLOCK_GetFllFreq()
690 MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
700 MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); in CLOCK_SetInternalRefClkConfig()
844 MCG->C2 &= ~MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
848 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
955 MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
969 MCG->C2 &= ~OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1244 if (MCG->C2 & MCG_C2_EREFS_MASK) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
Dsystem_MKW30Z4.c138 …MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_… in SystemInit()
160 …MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C… in SystemInit()
165 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ in SystemInit()
171 …MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C… in SystemInit()
189 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL in bypass mode */ in SystemInit()
227 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
277 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
Dsystem_MKW20Z4.c138 …MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_… in SystemInit()
160 …MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C… in SystemInit()
165 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ in SystemInit()
171 …MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C… in SystemInit()
189 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL in bypass mode */ in SystemInit()
227 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
277 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
Dsystem_MKW40Z4.c138 …MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_… in SystemInit()
160 …MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C… in SystemInit()
165 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ in SystemInit()
171 …MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C… in SystemInit()
189 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL in bypass mode */ in SystemInit()
227 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
277 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
613 if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) in CLOCK_GetFllFreq()
790 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
801 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
983 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
987 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1119 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1139 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1495 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
613 if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) in CLOCK_GetFllFreq()
790 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
801 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
983 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
987 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1119 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1139 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1495 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
692 if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) in CLOCK_GetFllFreq()
897 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
908 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
1088 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1092 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1261 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1281 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1638 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
659 if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) in CLOCK_GetFllFreq()
864 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
875 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
1055 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1059 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1228 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1248 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1605 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
698 if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) in CLOCK_GetFllFreq()
904 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
915 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
1097 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1101 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1270 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1290 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1647 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
698 if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) in CLOCK_GetFllFreq()
904 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
915 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
1097 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1101 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1270 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1290 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1647 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
710 assert((MCG->C2 & MCG_C2_IRCS_MASK) == 0U); in CLOCK_EnableUsbhs0PhyPllClock()
889 if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) in CLOCK_GetFllFreq()
1122 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
1133 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
1331 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1335 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1538 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1558 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
[all …]
/hal_nxp-2.7.6/mcux/drivers/imxrt6xx/
Dfsl_acmp.c421 base->C2 &= ~(tmp32); in ACMP_SetRoundRobinConfig()
435 tmp32 = (base->C2 & in ACMP_SetRoundRobinConfig()
442 base->C2 = tmp32; in ACMP_SetRoundRobinConfig()
459 uint32_t tmp32 = (base->C2 & ~(CMP_C2_ACOn_MASK | CMP_C2_CHnF_MASK)); in ACMP_SetRoundRobinPreState()
462 base->C2 = tmp32; in ACMP_SetRoundRobinPreState()
474 uint32_t tmp32 = (base->C2 & (~CMP_C2_CHnF_MASK)); in ACMP_ClearRoundRobinStatusFlags()
477 base->C2 = tmp32; in ACMP_ClearRoundRobinStatusFlags()
510 tmp32 = base->C2; in ACMP_EnableInterrupts()
513 base->C2 = tmp32; in ACMP_EnableInterrupts()
547 tmp32 = base->C2; in ACMP_DisableInterrupts()
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/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_acmp.c421 base->C2 &= ~(tmp32); in ACMP_SetRoundRobinConfig()
435 tmp32 = (base->C2 & in ACMP_SetRoundRobinConfig()
442 base->C2 = tmp32; in ACMP_SetRoundRobinConfig()
459 uint32_t tmp32 = (base->C2 & ~(CMP_C2_ACOn_MASK | CMP_C2_CHnF_MASK)); in ACMP_SetRoundRobinPreState()
462 base->C2 = tmp32; in ACMP_SetRoundRobinPreState()
474 uint32_t tmp32 = (base->C2 & (~CMP_C2_CHnF_MASK)); in ACMP_ClearRoundRobinStatusFlags()
477 base->C2 = tmp32; in ACMP_ClearRoundRobinStatusFlags()
510 tmp32 = base->C2; in ACMP_EnableInterrupts()
513 base->C2 = tmp32; in ACMP_EnableInterrupts()
547 tmp32 = base->C2; in ACMP_DisableInterrupts()
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/hal_nxp-2.7.6/mcux/devices/MIMXRT1176/
Dfsl_acmp.c421 base->C2 &= ~(tmp32); in ACMP_SetRoundRobinConfig()
435 tmp32 = (base->C2 & in ACMP_SetRoundRobinConfig()
442 base->C2 = tmp32; in ACMP_SetRoundRobinConfig()
459 uint32_t tmp32 = (base->C2 & ~(CMP_C2_ACOn_MASK | CMP_C2_CHnF_MASK)); in ACMP_SetRoundRobinPreState()
462 base->C2 = tmp32; in ACMP_SetRoundRobinPreState()
474 uint32_t tmp32 = (base->C2 & (~CMP_C2_CHnF_MASK)); in ACMP_ClearRoundRobinStatusFlags()
477 base->C2 = tmp32; in ACMP_ClearRoundRobinStatusFlags()
510 tmp32 = base->C2; in ACMP_EnableInterrupts()
513 base->C2 = tmp32; in ACMP_EnableInterrupts()
547 tmp32 = base->C2; in ACMP_DisableInterrupts()
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