| /hal_espressif-latest/components/hal/esp32s2/include/hal/ |
| D | memprot_peri_ll.h | 164 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_R, lr ? 1 : 0); in memprot_ll_peri1_rtcslow_set_read_perm()
165 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_R, hr ? 1 : 0); in memprot_ll_peri1_rtcslow_set_read_perm()
170 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_W, lw ? 1 : 0); in memprot_ll_peri1_rtcslow_set_write_perm()
171 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_W, hw ? 1 : 0); in memprot_ll_peri1_rtcslow_set_write_perm()
330 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R, lr ? 1 : 0); in memprot_ll_peri2_rtcslow_0_set_read_perm()
331 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R, hr ? 1 : 0); in memprot_ll_peri2_rtcslow_0_set_read_perm()
336 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W, lw ? 1 : 0); in memprot_ll_peri2_rtcslow_0_set_write_perm()
337 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W, hw ? 1 : 0); in memprot_ll_peri2_rtcslow_0_set_write_perm()
342 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F, lx ? 1 : 0); in memprot_ll_peri2_rtcslow_0_set_exec_perm()
343 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F, hx ? 1 : 0); in memprot_ll_peri2_rtcslow_0_set_exec_perm()
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| D | memprot_ll.h | 378 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_R, lr ? 1 : 0); in memprot_ll_iram0_sram_set_read_perm()
379 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_R, hr ? 1 : 0); in memprot_ll_iram0_sram_set_read_perm()
384 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_W, lw ? 1 : 0); in memprot_ll_iram0_sram_set_write_perm()
385 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_W, hw ? 1 : 0); in memprot_ll_iram0_sram_set_write_perm()
390 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_F, lx ? 1 : 0); in memprot_ll_iram0_sram_set_exec_perm()
391 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_F, hx ? 1 : 0); in memprot_ll_iram0_sram_set_exec_perm()
474 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_R, lr ? 1 : 0); in memprot_ll_iram0_rtcfast_set_read_perm()
475 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_R, hr ? 1 : 0); in memprot_ll_iram0_rtcfast_set_read_perm()
480 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_W, lw ? 1 : 0); in memprot_ll_iram0_rtcfast_set_write_perm()
481 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_W, hw ? 1 : 0); in memprot_ll_iram0_rtcfast_set_write_perm()
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| /hal_espressif-latest/components/esp_hw_support/port/esp32/ |
| D | cache_sram_mmu.c | 118 DPORT_REG_SET_FIELD(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_SRAM_PAGE_MODE, mask_s); in cache_sram_mmu_set()
120 DPORT_REG_SET_FIELD(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_SRAM_PAGE_MODE, mask_s); in cache_sram_mmu_set()
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| D | rtc_sleep.c | 73 DPORT_REG_SET_FIELD(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK, ~cfg.cpu_pd); in rtc_sleep_pd()
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| /hal_espressif-latest/components/soc/esp32c6/include/soc/ |
| D | dport_access.h | 58 #define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) <<… macro
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| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | dport_access.h | 55 #define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) <<… macro
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| /hal_espressif-latest/components/soc/esp32h2/include/soc/ |
| D | dport_access.h | 57 #define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) <<… macro
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| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | dport_access.h | 58 #define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) <<… macro
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| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | dport_access.h | 58 #define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) <<… macro
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| /hal_espressif-latest/components/soc/esp32s2/include/soc/ |
| D | dport_access.h | 56 #define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) <<… macro
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| /hal_espressif-latest/components/soc/esp32/include/soc/ |
| D | dport_access.h | 149 #define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) <<… macro
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| /hal_espressif-latest/components/esp_system/port/soc/esp32s2/ |
| D | clk.c | 311 DPORT_REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 0); in esp_perip_clk_init()
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