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Searched refs:CACHE_BUS_IBUS2 (Results 1 – 9 of 9) sorted by relevance

/hal_espressif-latest/components/hal/esp32/include/hal/
Dcache_ll.h104 mask |= CACHE_BUS_IBUS2; in cache_ll_l1_get_bus()
107 mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0; in cache_ll_l1_get_bus()
111 mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0; in cache_ll_l1_get_bus()
144 bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0; in cache_ll_l1_enable_bus()
153 bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0; in cache_ll_l1_enable_bus()
178 mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0; in cache_ll_l1_get_enabled_bus()
186 mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0; in cache_ll_l1_get_enabled_bus()
211 bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0; in cache_ll_l1_disable_bus()
220 bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0; in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dcache_ll.h23 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_IBUS2
89 mask |= CACHE_BUS_IBUS2; in cache_ll_l1_get_bus()
118 ibus_mask |= (mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0; in cache_ll_l1_enable_bus()
142 ibus_mask |= (mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0; in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dcache_ll.h70 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
92 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dcache_ll.h70 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
92 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dcache_ll.h96 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
118 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dcache_ll.h97 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
119 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/include/hal/
Dcache_types.h31 CACHE_BUS_IBUS2 = BIT(2), enumerator
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dcache_ll.h108 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
169 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/esp_mm/port/esp32s2/
Dext_mem_layout.c30 .bus_id = CACHE_BUS_IBUS2,