Home
last modified time | relevance | path

Searched refs:PCR_SYSCLK_CONF_REG (Results 1 – 5 of 5) sorted by relevance

/hal_espressif-3.7.0/tools/esptool_py/esptool/targets/
Desp32c5.py23 PCR_SYSCLK_CONF_REG = 0x60096110 variable in ESP32C5ROM
67 self.read_reg(self.PCR_SYSCLK_CONF_REG) & self.PCR_SYSCLK_XTAL_FREQ_V
/hal_espressif-3.7.0/tools/esptool_py/flasher_stub/
Dstub_flasher.c79 pcr_sysclk_conf_reg = READ_REG(PCR_SYSCLK_CONF_REG); in set_max_cpu_freq()
80 …WRITE_REG(PCR_SYSCLK_CONF_REG, (pcr_sysclk_conf_reg & ~PCR_SOC_CLK_SEL_M) | (PCR_SOC_CLK_MAX << PC… in set_max_cpu_freq()
98 …WRITE_REG(PCR_SYSCLK_CONF_REG, (READ_REG(PCR_SYSCLK_CONF_REG) & ~PCR_SOC_CLK_SEL_M) | (pcr_sysclk_… in reset_cpu_freq()
/hal_espressif-3.7.0/tools/esptool_py/flasher_stub/include/
Dsoc_support.h460 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) macro
468 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) macro
476 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) macro
/hal_espressif-3.7.0/components/soc/esp32c6/include/soc/
Dpcr_reg.h1599 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) macro
/hal_espressif-3.7.0/components/soc/esp32h2/include/soc/
Dpcr_reg.h1837 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) macro