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Searched refs:REG_WRITE (Results 1 – 25 of 106) sorted by relevance

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/hal_espressif-3.6.0/components/hal/esp32c3/include/hal/
Dhmac_ll.h46 REG_WRITE(HMAC_SET_START_REG, 1); in hmac_ll_start()
59 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP); in hmac_ll_config_output()
62 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE); in hmac_ll_config_output()
65 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG); in hmac_ll_config_output()
68 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL); in hmac_ll_config_output()
80 REG_WRITE(HMAC_SET_PARA_KEY_REG, key_id); in hmac_ll_config_hw_key_id()
90 REG_WRITE(HMAC_SET_PARA_FINISH_REG, 1); in hmac_ll_config_finish()
124 REG_WRITE(HMAC_WDATA_BASE + (i * REG_WIDTH), block[i]); in hmac_ll_write_block_512()
127 REG_WRITE(HMAC_SET_MESSAGE_ONE_REG, 1); in hmac_ll_write_block_512()
146 REG_WRITE(HMAC_SET_INVALIDATE_DS_REG, 1); in hmac_ll_clean()
[all …]
Dsha_ll.h32 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_block()
33 REG_WRITE(SHA_START_REG, 1); in sha_ll_start_block()
43 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_block()
44 REG_WRITE(SHA_CONTINUE_REG, 1); in sha_ll_continue_block()
54 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_dma()
55 REG_WRITE(SHA_DMA_START_REG, 1); in sha_ll_start_dma()
65 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_dma()
66 REG_WRITE(SHA_DMA_CONTINUE_REG, 1); in sha_ll_continue_dma()
89 REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks); in sha_ll_set_block_num()
115 REG_WRITE(&reg_addr_buf[i], data_words[i]); in sha_ll_fill_text_block()
[all …]
Daes_ll.h53 REG_WRITE(AES_KEY_BASE + i * 4, key_word); in aes_ll_write_key()
71 REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); in aes_ll_set_mode()
85 REG_WRITE(AES_TEXT_IN_BASE + i * 4, input_word); in aes_ll_write_block()
112 REG_WRITE(AES_TRIGGER_REG, 1); in aes_ll_start_transform()
136 REG_WRITE(AES_BLOCK_MODE_REG, mode); in aes_ll_set_block_mode()
147 REG_WRITE(AES_INC_SEL_REG, 0); in aes_ll_set_inc()
156 REG_WRITE(AES_DMA_EXIT_REG, 0); in aes_ll_dma_exit()
168 REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); in aes_ll_set_num_blocks()
182 REG_WRITE(&reg_addr_buf[i], iv_word); in aes_ll_set_iv()
208 REG_WRITE(AES_DMA_ENABLE_REG, enable); in aes_ll_dma_enable()
[all …]
Dspi_flash_encrypted_ll.h71 REG_WRITE(AES_XTS_DESTINATION_REG, type); in spi_flash_encrypt_ll_type()
82 REG_WRITE(AES_XTS_SIZE_REG, size >> 5); in spi_flash_encrypt_ll_buffer_length()
106 REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr); in spi_flash_encrypt_ll_address_save()
114 REG_WRITE(AES_XTS_TRIGGER_REG, 1); in spi_flash_encrypt_ll_calculate_start()
131 REG_WRITE(AES_XTS_RELEASE_REG, 1); in spi_flash_encrypt_ll_done()
141 REG_WRITE(AES_XTS_DESTROY_REG, 1); in spi_flash_encrypt_ll_destroy()
Dds_ll.h35 REG_WRITE(DS_SET_START_REG, 1); in ds_ll_start()
73 REG_WRITE(DS_IV_BASE + (i * 4) , iv[i]); in ds_ll_configure_iv()
122 REG_WRITE(DS_SET_ME_REG, 1); in ds_ll_start_sign()
169 REG_WRITE(DS_SET_FINISH_REG, 1); in ds_ll_finish()
/hal_espressif-3.6.0/components/hal/esp32h2/include/hal/
Dhmac_ll.h46 REG_WRITE(HMAC_SET_START_REG, 1); in hmac_ll_start()
59 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP); in hmac_ll_config_output()
62 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE); in hmac_ll_config_output()
65 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG); in hmac_ll_config_output()
68 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL); in hmac_ll_config_output()
80 REG_WRITE(HMAC_SET_PARA_KEY_REG, key_id); in hmac_ll_config_hw_key_id()
90 REG_WRITE(HMAC_SET_PARA_FINISH_REG, 1); in hmac_ll_config_finish()
124 REG_WRITE(HMAC_WDATA_BASE + (i * REG_WIDTH), block[i]); in hmac_ll_write_block_512()
127 REG_WRITE(HMAC_SET_MESSAGE_ONE_REG, 1); in hmac_ll_write_block_512()
146 REG_WRITE(HMAC_SET_INVALIDATE_DS_REG, 1); in hmac_ll_clean()
[all …]
Dsha_ll.h32 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_block()
33 REG_WRITE(SHA_START_REG, 1); in sha_ll_start_block()
43 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_block()
44 REG_WRITE(SHA_CONTINUE_REG, 1); in sha_ll_continue_block()
54 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_dma()
55 REG_WRITE(SHA_DMA_START_REG, 1); in sha_ll_start_dma()
65 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_dma()
66 REG_WRITE(SHA_DMA_CONTINUE_REG, 1); in sha_ll_continue_dma()
89 REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks); in sha_ll_set_block_num()
115 REG_WRITE(&reg_addr_buf[i], data_words[i]); in sha_ll_fill_text_block()
[all …]
Daes_ll.h53 REG_WRITE(AES_KEY_BASE + i * 4, key_word); in aes_ll_write_key()
71 REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); in aes_ll_set_mode()
85 REG_WRITE(AES_TEXT_IN_BASE + i * 4, input_word); in aes_ll_write_block()
112 REG_WRITE(AES_TRIGGER_REG, 1); in aes_ll_start_transform()
136 REG_WRITE(AES_BLOCK_MODE_REG, mode); in aes_ll_set_block_mode()
147 REG_WRITE(AES_INC_SEL_REG, 0); in aes_ll_set_inc()
156 REG_WRITE(AES_DMA_EXIT_REG, 0); in aes_ll_dma_exit()
168 REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); in aes_ll_set_num_blocks()
182 REG_WRITE(&reg_addr_buf[i], iv_word); in aes_ll_set_iv()
208 REG_WRITE(AES_DMA_ENABLE_REG, enable); in aes_ll_dma_enable()
[all …]
Dspi_flash_encrypted_ll.h71 REG_WRITE(AES_XTS_DESTINATION_REG, type); in spi_flash_encrypt_ll_type()
82 REG_WRITE(AES_XTS_SIZE_REG, size >> 5); in spi_flash_encrypt_ll_buffer_length()
106 REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr); in spi_flash_encrypt_ll_address_save()
114 REG_WRITE(AES_XTS_TRIGGER_REG, 1); in spi_flash_encrypt_ll_calculate_start()
131 REG_WRITE(AES_XTS_RELEASE_REG, 1); in spi_flash_encrypt_ll_done()
141 REG_WRITE(AES_XTS_DESTROY_REG, 1); in spi_flash_encrypt_ll_destroy()
Dds_ll.h35 REG_WRITE(DS_SET_START_REG, 1); in ds_ll_start()
73 REG_WRITE(DS_IV_BASE + (i * 4) , iv[i]); in ds_ll_configure_iv()
122 REG_WRITE(DS_SET_ME_REG, 1); in ds_ll_start_sign()
169 REG_WRITE(DS_SET_FINISH_REG, 1); in ds_ll_finish()
/hal_espressif-3.6.0/components/hal/esp32s3/include/hal/
Dhmac_ll.h34 REG_WRITE(HMAC_SET_START_REG, 1); in hmac_ll_start()
47 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_UP); in hmac_ll_config_output()
50 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_DIGITAL_SIGNATURE); in hmac_ll_config_output()
53 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_JTAG); in hmac_ll_config_output()
56 REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_ALL); in hmac_ll_config_output()
68 REG_WRITE(HMAC_SET_PARA_KEY_REG, key_id); in hmac_ll_config_hw_key_id()
78 REG_WRITE(HMAC_SET_PARA_FINISH_REG, 1); in hmac_ll_config_finish()
112 REG_WRITE(HMAC_WDATA_BASE + (i * REG_WIDTH), block[i]); in hmac_ll_write_block_512()
115 REG_WRITE(HMAC_SET_MESSAGE_ONE_REG, 1); in hmac_ll_write_block_512()
134 REG_WRITE(HMAC_SET_INVALIDATE_DS_REG, 1); in hmac_ll_clean()
[all …]
Dsha_ll.h33 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_block()
34 REG_WRITE(SHA_START_REG, 1); in sha_ll_start_block()
44 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_block()
45 REG_WRITE(SHA_CONTINUE_REG, 1); in sha_ll_continue_block()
55 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_dma()
56 REG_WRITE(SHA_DMA_START_REG, 1); in sha_ll_start_dma()
66 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_dma()
67 REG_WRITE(SHA_DMA_CONTINUE_REG, 1); in sha_ll_continue_dma()
90 REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks); in sha_ll_set_block_num()
116 REG_WRITE(&reg_addr_buf[i], data_words[i]); in sha_ll_fill_text_block()
[all …]
Daes_ll.h53 REG_WRITE(AES_KEY_BASE + i * 4, key_word); in aes_ll_write_key()
71 REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); in aes_ll_set_mode()
85 REG_WRITE(AES_TEXT_IN_BASE + i * 4, input_word); in aes_ll_write_block()
112 REG_WRITE(AES_TRIGGER_REG, 1); in aes_ll_start_transform()
136 REG_WRITE(AES_BLOCK_MODE_REG, mode); in aes_ll_set_block_mode()
147 REG_WRITE(AES_INC_SEL_REG, 0); in aes_ll_set_inc()
156 REG_WRITE(AES_DMA_EXIT_REG, 0); in aes_ll_dma_exit()
168 REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); in aes_ll_set_num_blocks()
182 REG_WRITE(&reg_addr_buf[i], iv_word); in aes_ll_set_iv()
208 REG_WRITE(AES_DMA_ENABLE_REG, enable); in aes_ll_dma_enable()
[all …]
Dspi_flash_encrypted_ll.h71 REG_WRITE(AES_XTS_DESTINATION_REG, type); in spi_flash_encrypt_ll_type()
82 REG_WRITE(AES_XTS_SIZE_REG, size >> 5); in spi_flash_encrypt_ll_buffer_length()
106 REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr); in spi_flash_encrypt_ll_address_save()
114 REG_WRITE(AES_XTS_TRIGGER_REG, 1); in spi_flash_encrypt_ll_calculate_start()
131 REG_WRITE(AES_XTS_RELEASE_REG, 1); in spi_flash_encrypt_ll_done()
141 REG_WRITE(AES_XTS_DESTROY_REG, 1); in spi_flash_encrypt_ll_destroy()
Dds_ll.h22 REG_WRITE(DS_SET_START_REG, 1); in ds_ll_start()
60 REG_WRITE(DS_IV_BASE + (i * 4), iv[i]); in ds_ll_configure_iv()
110 REG_WRITE(DS_SET_ME_REG, 1); in ds_ll_start_sign()
156 REG_WRITE(DS_SET_FINISH_REG, 1); in ds_ll_finish()
/hal_espressif-3.6.0/components/hal/esp32s2/include/hal/
Dsha_ll.h33 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_block()
34 REG_WRITE(SHA_START_REG, 1); in sha_ll_start_block()
44 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_block()
45 REG_WRITE(SHA_CONTINUE_REG, 1); in sha_ll_continue_block()
55 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_start_dma()
56 REG_WRITE(SHA_DMA_START_REG, 1); in sha_ll_start_dma()
66 REG_WRITE(SHA_MODE_REG, sha_type); in sha_ll_continue_dma()
67 REG_WRITE(SHA_DMA_CONTINUE_REG, 1); in sha_ll_continue_dma()
90 REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks); in sha_ll_set_block_num()
116 REG_WRITE(&reg_addr_buf[i], data_words[i]); in sha_ll_fill_text_block()
[all …]
Daes_ll.h54 REG_WRITE(AES_KEY_BASE + i * 4, key_word); in aes_ll_write_key()
72 REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); in aes_ll_set_mode()
86 REG_WRITE(AES_TEXT_IN_BASE + i * 4, input_word); in aes_ll_write_block()
114 REG_WRITE(AES_TRIGGER_REG, 1); in aes_ll_start_transform()
124 REG_WRITE(AES_CONTINUE_REG, 1); in aes_ll_cont_transform()
147 REG_WRITE(AES_BLOCK_MODE_REG, mode); in aes_ll_set_block_mode()
158 REG_WRITE(AES_INC_SEL_REG, 0); in aes_ll_set_inc()
167 REG_WRITE(AES_DMA_EXIT_REG, 0); in aes_ll_dma_exit()
179 REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); in aes_ll_set_num_blocks()
193 REG_WRITE(&reg_addr_buf[i], iv_word); in aes_ll_set_iv()
[all …]
Dspi_flash_encrypted_ll.h81 REG_WRITE(AES_XTS_DESTINATION_REG, type); in spi_flash_encrypt_ll_type()
92 REG_WRITE(AES_XTS_SIZE_REG, size >> 5); in spi_flash_encrypt_ll_buffer_length()
115 REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr); in spi_flash_encrypt_ll_address_save()
123 REG_WRITE(AES_XTS_TRIGGER_REG, 1); in spi_flash_encrypt_ll_calculate_start()
140 REG_WRITE(AES_XTS_RELEASE_REG, 1); in spi_flash_encrypt_ll_done()
150 REG_WRITE(AES_XTS_DESTROY_REG, 1); in spi_flash_encrypt_ll_destroy()
/hal_espressif-3.6.0/components/mbedtls/port/esp32c3/
Dbignum.c112 REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); in start_op()
117 REG_WRITE(op_reg, 1); in start_op()
128 REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); in wait_op_complete()
146 REG_WRITE(RSA_LENGTH_REG, (num_words - 1)); in esp_mpi_mul_mpi_mod_hw_op()
153 REG_WRITE(RSA_M_DASH_REG, Mprime); in esp_mpi_mul_mpi_mod_hw_op()
164 REG_WRITE(RSA_LENGTH_REG, (num_words - 1)); in esp_mpi_exp_mpi_mod_hw_op()
171 REG_WRITE(RSA_M_DASH_REG, Mprime); in esp_mpi_exp_mpi_mod_hw_op()
174 REG_WRITE(RSA_CONSTANT_TIME_REG, 0); in esp_mpi_exp_mpi_mod_hw_op()
175 REG_WRITE(RSA_SEARCH_ENABLE_REG, 1); in esp_mpi_exp_mpi_mod_hw_op()
176 REG_WRITE(RSA_SEARCH_POS_REG, y_bits - 1); in esp_mpi_exp_mpi_mod_hw_op()
[all …]
/hal_espressif-3.6.0/components/mbedtls/port/esp32h2/
Dbignum.c112 REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); in start_op()
117 REG_WRITE(op_reg, 1); in start_op()
128 REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); in wait_op_complete()
146 REG_WRITE(RSA_LENGTH_REG, (num_words - 1)); in esp_mpi_mul_mpi_mod_hw_op()
153 REG_WRITE(RSA_M_DASH_REG, Mprime); in esp_mpi_mul_mpi_mod_hw_op()
164 REG_WRITE(RSA_LENGTH_REG, (num_words - 1)); in esp_mpi_exp_mpi_mod_hw_op()
171 REG_WRITE(RSA_M_DASH_REG, Mprime); in esp_mpi_exp_mpi_mod_hw_op()
174 REG_WRITE(RSA_CONSTANT_TIME_REG, 0); in esp_mpi_exp_mpi_mod_hw_op()
175 REG_WRITE(RSA_SEARCH_ENABLE_REG, 1); in esp_mpi_exp_mpi_mod_hw_op()
176 REG_WRITE(RSA_SEARCH_POS_REG, y_bits - 1); in esp_mpi_exp_mpi_mod_hw_op()
[all …]
/hal_espressif-3.6.0/components/esp_timer/src/
Desp_timer_impl_frc_legacy.c166 REG_WRITE(FRC_TIMER_LOAD_REG(1), REG_READ(FRC_TIMER_COUNT_REG(1)) - ALARM_OVERFLOW_VAL); in timer_count_reload()
250 REG_WRITE(FRC_TIMER_ALARM_REG(1), alarm_reg_val);
282 REG_WRITE(FRC_TIMER_INT_REG(1), FRC_TIMER_INT_CLR);
285 REG_WRITE(FRC_TIMER_ALARM_REG(1), ALARM_OVERFLOW_VAL);
325 REG_WRITE(FRC_TIMER_ALARM_REG(1), new_alarm_val);
326 REG_WRITE(FRC_TIMER_LOAD_REG(1), 0);
361 REG_WRITE(FRC_TIMER_ALARM_REG(1), 0);
362 REG_WRITE(FRC_TIMER_LOAD_REG(1), 0);
388 REG_WRITE(FRC_TIMER_ALARM_REG(1), ALARM_OVERFLOW_VAL);
389 REG_WRITE(FRC_TIMER_LOAD_REG(1), 0);
[all …]
Desp_timer_impl_lac.c140 REG_WRITE(UPDATE_REG, 1); in esp_timer_impl_get_counter_reg()
185 REG_WRITE(ALARM_LO_REG, alarm.lo); in esp_timer_impl_set_alarm_id()
186 REG_WRITE(ALARM_HI_REG, alarm.hi); in esp_timer_impl_set_alarm_id()
211 REG_WRITE(INT_CLR_REG, TIMG_LACT_INT_CLR); in timer_alarm_isr()
230 REG_WRITE(LOAD_LO_REG, dst.lo); in esp_timer_impl_advance()
231 REG_WRITE(LOAD_HI_REG, dst.hi); in esp_timer_impl_advance()
232 REG_WRITE(LOAD_REG, 1); in esp_timer_impl_advance()
240 REG_WRITE(CONFIG_REG, 0); in esp_timer_impl_early_init()
241 REG_WRITE(LOAD_LO_REG, 0); in esp_timer_impl_early_init()
242 REG_WRITE(LOAD_HI_REG, 0); in esp_timer_impl_early_init()
[all …]
/hal_espressif-3.6.0/components/efuse/esp32/
Desp_efuse_utility.c71 REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ); in esp_efuse_utility_clear_program_registers()
93 REG_WRITE(range_write_addr_blocks[num_block].start + k * 4, out_buf[k]); in esp_efuse_utility_burn_chip()
107 REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_WRITE); in esp_efuse_utility_burn_chip()
108 REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_PGM); in esp_efuse_utility_burn_chip()
110 REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ); in esp_efuse_utility_burn_chip()
111 REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_READ); in esp_efuse_utility_burn_chip()
153 REG_WRITE(addr_wr_block, 0); in read_w_data_and_check_fill()
206 … REG_WRITE(range_write_addr_blocks[num_block].start + (num_reg + r) * 4, reg[r]); in esp_efuse_utility_apply_new_coding_scheme()
220 REG_WRITE(range_write_addr_blocks[num_block].start + i * 4, buf_32[i]); in esp_efuse_utility_apply_new_coding_scheme()
221 … REG_WRITE(range_write_addr_blocks[num_block].start + (i + 4) * 4, buf_32[i]); in esp_efuse_utility_apply_new_coding_scheme()
/hal_espressif-3.6.0/components/driver/test/dac_dma_test/
Dtest_esp32s2.c44 #define SET_BREAK_POINT(flag) REG_WRITE(SYSCON_DATE_REG, flag)
138 REG_WRITE(SPI_DMA_INT_CLR_REG(3), int_st); in dac_dma_isr()
240 REG_WRITE(SPI_DMA_INT_CLR_REG(3), status); in adc_dac_dma_isr_default()
250 REG_WRITE(SPI_DMA_INT_ENA_REG(3), 0); in adc_dac_dma_isr_ensure_installed()
251 REG_WRITE(SPI_DMA_INT_CLR_REG(3), UINT32_MAX); in adc_dac_dma_isr_ensure_installed()
312 REG_WRITE(SPI_DMA_INT_CLR_REG(3), 0xFFFFFFFF); in adc_dac_dma_linker_start()
313 REG_WRITE(SPI_DMA_INT_ENA_REG(3), int_msk | REG_READ(SPI_DMA_INT_ENA_REG(3))); in adc_dac_dma_linker_start()
349 REG_WRITE(SPI_DMA_INT_CLR_REG(3), 0xFFFFFFFF); in adc_dac_dma_linker_deinit()
350 REG_WRITE(SPI_DMA_INT_ENA_REG(3), 0); in adc_dac_dma_linker_deinit()
/hal_espressif-3.6.0/components/spi_flash/esp32/
Dspi_flash_rom_patch.c101 REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WREN); in esp_rom_spiflash_unlock()
108 REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WRDI); in esp_rom_spiflash_unlock()
292 …REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_… in esp_rom_spiflash_read_data()
294 REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR); in esp_rom_spiflash_read_data()
305 …REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_… in esp_rom_spiflash_read_data()
306 REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR); in esp_rom_spiflash_read_data()
566 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xEB); in esp_rom_spiflash_read()
574 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xBB); in esp_rom_spiflash_read()
584 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x6B); in esp_rom_spiflash_read()
587 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x3B); in esp_rom_spiflash_read()
[all …]

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