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Searched refs:DR_REG_ASSIST_DEBUG_BASE (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dassist_debug_reg.h23 #define ASSIST_DEBUG_CORE_0_INTERRUPT_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
97 #define ASSIST_DEBUG_CORE_0_INTERRUPT_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
171 #define ASSIST_DEBUG_CORE_0_INTERRUPT_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
245 #define ASSIST_DEBUG_CORE_0_INTERRUPT_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xC)
319 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
327 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
335 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
343 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1C)
351 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
359 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
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Dsoc.h110 #define DR_REG_ASSIST_DEBUG_BASE 0x600CE000 macro
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dassist_debug_reg.h22 #define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000)
96 #define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x004)
170 #define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x008)
244 #define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x00C)
318 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x010)
326 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x014)
334 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x018)
342 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x01C)
350 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x020)
358 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x024)
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Dsoc.h43 #define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 macro
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dassist_debug_reg.h22 #define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000)
96 #define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x004)
170 #define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x008)
244 #define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x00C)
318 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x010)
326 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x014)
334 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x018)
342 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x01C)
350 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x020)
358 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x024)
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Dsoc.h38 #define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 macro
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dassist_debug_reg.h1 #define ASSIST_DEBUG_BASE DR_REG_ASSIST_DEBUG_BASE
Dsoc.h41 #define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000 macro