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Searched refs:sam_cfg (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/drivers/can/
Dcan_sam.c75 const struct can_sam_config *sam_cfg = mcan_cfg->custom; in can_sam_get_core_clock() local
77 *rate = SOC_ATMEL_SAM_UPLLCK_FREQ_HZ / (sam_cfg->divider); in can_sam_get_core_clock()
82 static void can_sam_clock_enable(const struct can_sam_config *sam_cfg) in can_sam_clock_enable() argument
84 REG_PMC_PCK5 = PMC_PCK_CSS_UPLL_CLK | PMC_PCK_PRES(sam_cfg->divider - 1); in can_sam_clock_enable()
89 (clock_control_subsys_t)&sam_cfg->clock_cfg); in can_sam_clock_enable()
95 const struct can_sam_config *sam_cfg = mcan_cfg->custom; in can_sam_init() local
98 can_sam_clock_enable(sam_cfg); in can_sam_init()
100 ret = pinctrl_apply_state(sam_cfg->pcfg, PINCTRL_STATE_DEFAULT); in can_sam_init()
106 uint32_t mrba = sam_cfg->mram & 0xFFFF0000; in can_sam_init()
109 sys_write32((sys_read32(sam_cfg->dma_base) & 0x0000FFFF) | mrba, sam_cfg->dma_base); in can_sam_init()
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Dcan_sam0.c97 const struct can_sam0_config *sam_cfg = mcan_cfg->custom; in can_sam0_get_core_clock() local
101 *rate = SOC_ATMEL_SAM0_DFLL48_FREQ_HZ / (sam_cfg->divider); in can_sam0_get_core_clock()
104 *rate = SOC_ATMEL_SAM0_OSC48M_FREQ_HZ / (sam_cfg->divider); in can_sam0_get_core_clock()
136 const struct can_sam0_config *sam_cfg = mcan_cfg->custom; in can_sam0_init() local
139 can_sam0_clock_enable(sam_cfg); in can_sam0_init()
141 ret = pinctrl_apply_state(sam_cfg->pcfg, PINCTRL_STATE_DEFAULT); in can_sam0_init()
147 ret = can_mcan_configure_mram(dev, 0U, sam_cfg->mram); in can_sam0_init()
159 sam_cfg->config_irq(); in can_sam0_init()