| /Zephyr-latest/include/zephyr/ |
| D | irq_multilevel.h | 27 uint32_t irq; member
42 uint32_t irq: CONFIG_1ST_LEVEL_INTERRUPT_BITS + CONFIG_2ND_LEVEL_INTERRUPT_BITS; member
48 uint32_t irq: CONFIG_1ST_LEVEL_INTERRUPT_BITS; member
54 static inline uint32_t _z_l1_irq(_z_irq_t irq) in _z_l1_irq() argument
56 return irq.bits.l1; in _z_l1_irq()
59 static inline uint32_t _z_l2_irq(_z_irq_t irq) in _z_l2_irq() argument
61 return irq.bits.l2 - 1; in _z_l2_irq()
64 static inline uint32_t _z_l3_irq(_z_irq_t irq) in _z_l3_irq() argument
66 return irq.bits.l3 - 1; in _z_l3_irq()
90 static inline unsigned int irq_get_level(unsigned int irq) in irq_get_level() argument
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| /Zephyr-latest/soc/common/riscv-privileged/ |
| D | soc_common_irq.c | 20 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
22 riscv_clic_irq_enable(irq); in arch_irq_enable()
25 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
27 riscv_clic_irq_disable(irq); in arch_irq_disable()
30 int arch_irq_is_enabled(unsigned int irq) in arch_irq_is_enabled() argument
32 return riscv_clic_irq_is_enabled(irq); in arch_irq_is_enabled()
35 void z_riscv_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_riscv_irq_priority_set() argument
37 riscv_clic_irq_priority_set(irq, prio, flags); in z_riscv_irq_priority_set()
40 void z_riscv_irq_vector_set(unsigned int irq) in z_riscv_irq_vector_set() argument
43 riscv_clic_irq_vector_set(irq); in z_riscv_irq_vector_set()
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| /Zephyr-latest/arch/arc/core/ |
| D | irq_manage.c | 138 void arch_irq_enable(unsigned int irq);
146 void arch_irq_disable(unsigned int irq);
154 int arch_irq_is_enabled(unsigned int irq);
161 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
163 if (IRQ_IS_COMMON(irq)) { in arch_irq_enable()
164 z_arc_connect_idu_set_mask(IRQ_NUM_TO_IDU_NUM(irq), 0x0); in arch_irq_enable()
166 z_arc_v2_irq_unit_int_enable(irq); in arch_irq_enable()
170 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
172 if (IRQ_IS_COMMON(irq)) { in arch_irq_disable()
173 z_arc_connect_idu_set_mask(IRQ_NUM_TO_IDU_NUM(irq), 0x1); in arch_irq_disable()
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| /Zephyr-latest/subsys/testsuite/include/zephyr/ |
| D | interrupt_util.h | 60 static inline void trigger_irq(int irq) in trigger_irq() argument
62 printk("Triggering irq : %d\n", irq); in trigger_irq()
67 NVIC_SetPendingIRQ(irq); in trigger_irq()
69 NVIC->STIR = irq; in trigger_irq()
77 static inline void trigger_irq(int irq) in trigger_irq() argument
79 printk("Triggering irq : %d\n", irq); in trigger_irq()
82 zassert_true(irq <= 15, "%u is not a valid SGI interrupt ID", irq); in trigger_irq()
89 sys_write32(GICD_SGIR_TGTFILT_REQONLY | GICD_SGIR_SGIINTID(irq), in trigger_irq()
95 gic_raise_sgi(irq, mpidr, BIT(aff0)); in trigger_irq()
100 static inline void trigger_irq(int irq) in trigger_irq() argument
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_system_apic.c | 22 #define IS_IOAPIC_IRQ(irq) ((irq) < z_loapic_irq_base()) argument
46 void z_irq_controller_irq_config(unsigned int vector, unsigned int irq, in z_irq_controller_irq_config() argument
49 __ASSERT(irq <= HARDWARE_IRQ_LIMIT, "invalid irq line"); in z_irq_controller_irq_config()
51 if (IS_IOAPIC_IRQ(irq)) { in z_irq_controller_irq_config()
52 z_ioapic_irq_set(irq, vector, flags); in z_irq_controller_irq_config()
54 z_loapic_int_vec_set(irq - z_loapic_irq_base(), vector); in z_irq_controller_irq_config()
73 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
75 if (IS_IOAPIC_IRQ(irq)) { in arch_irq_enable()
76 z_ioapic_irq_enable(irq); in arch_irq_enable()
78 z_loapic_irq_enable(irq - z_loapic_irq_base()); in arch_irq_enable()
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| D | intc_swerv_pic.c | 57 void swerv_pic_irq_enable(uint32_t irq) in swerv_pic_irq_enable() argument
61 if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) { in swerv_pic_irq_enable()
66 swerv_pic_write(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ), 1); in swerv_pic_irq_enable()
70 void swerv_pic_irq_disable(uint32_t irq) in swerv_pic_irq_disable() argument
74 if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) { in swerv_pic_irq_disable()
79 swerv_pic_write(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ), 0); in swerv_pic_irq_disable()
83 int swerv_pic_irq_is_enabled(uint32_t irq) in swerv_pic_irq_is_enabled() argument
85 if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) { in swerv_pic_irq_is_enabled()
89 return swerv_pic_read(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ)) in swerv_pic_irq_is_enabled()
93 void swerv_pic_set_priority(uint32_t irq, uint32_t priority) in swerv_pic_set_priority() argument
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| D | intc_ioapic.c | 99 #define BIT_POS_FOR_IRQ_OPTION(irq, option) ((irq) * BITS_PER_IRQ + (option)) argument
112 static void ioApicRedSetHi(unsigned int irq, uint32_t upper32);
113 static void ioApicRedSetLo(unsigned int irq, uint32_t lower32);
114 static uint32_t ioApicRedGetLo(unsigned int irq);
115 static void IoApicRedUpdateLo(unsigned int irq, uint32_t value,
195 void z_ioapic_irq_enable(unsigned int irq) in z_ioapic_irq_enable() argument
197 IoApicRedUpdateLo(irq, 0, IOAPIC_INT_MASK); in z_ioapic_irq_enable()
207 void z_ioapic_irq_disable(unsigned int irq) in z_ioapic_irq_disable() argument
209 IoApicRedUpdateLo(irq, IOAPIC_INT_MASK, IOAPIC_INT_MASK); in z_ioapic_irq_disable()
216 void store_flags(unsigned int irq, uint32_t flags) in store_flags() argument
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| D | intc_vim.c | 52 void z_vim_irq_eoi(unsigned int irq) in z_vim_irq_eoi() argument
64 void z_vim_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_vim_irq_priority_set() argument
68 if (irq > CONFIG_NUM_IRQS || prio > VIM_PRI_INT_MAX || in z_vim_irq_priority_set()
71 __func__, irq, prio, flags); in z_vim_irq_priority_set()
75 sys_write8(prio, VIM_PRI_INT(irq)); in z_vim_irq_priority_set()
77 irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq); in z_vim_irq_priority_set()
78 irq_bit_num = VIM_GET_IRQ_BIT_NUM(irq); in z_vim_irq_priority_set()
91 void z_vim_irq_enable(unsigned int irq) in z_vim_irq_enable() argument
95 if (irq > CONFIG_NUM_IRQS) { in z_vim_irq_enable()
96 LOG_ERR("%s: Invalid irq number = %u\n", __func__, irq); in z_vim_irq_enable()
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| D | intc_dw_ace.c | 74 static inline bool is_dw_irq(uint32_t irq) in is_dw_irq() argument
76 if (((irq & XTENSA_IRQ_NUM_MASK) == ACE_INTC_IRQ) in is_dw_irq()
77 && ((irq & ~XTENSA_IRQ_NUM_MASK) != 0)) { in is_dw_irq()
84 void dw_ace_irq_enable(const struct device *dev, uint32_t irq) in dw_ace_irq_enable() argument
88 if (is_dw_irq(irq)) { in dw_ace_irq_enable()
92 ACE_INTC[i].irq_inten_l |= BIT(ACE_IRQ_FROM_ZEPHYR(irq)); in dw_ace_irq_enable()
93 ACE_INTC[i].irq_intmask_l &= ~BIT(ACE_IRQ_FROM_ZEPHYR(irq)); in dw_ace_irq_enable()
95 } else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) { in dw_ace_irq_enable()
96 xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)); in dw_ace_irq_enable()
100 void dw_ace_irq_disable(const struct device *dev, uint32_t irq) in dw_ace_irq_disable() argument
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| D | intc_nrfx_clic.c | 11 void riscv_clic_irq_enable(uint32_t irq) in riscv_clic_irq_enable() argument
13 nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, irq, true); in riscv_clic_irq_enable()
16 void riscv_clic_irq_disable(uint32_t irq) in riscv_clic_irq_disable() argument
18 nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, irq, false); in riscv_clic_irq_disable()
21 int riscv_clic_irq_is_enabled(uint32_t irq) in riscv_clic_irq_is_enabled() argument
23 return nrf_vpr_clic_int_enable_check(NRF_VPRCLIC, irq); in riscv_clic_irq_is_enabled()
26 void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags) in riscv_clic_irq_priority_set() argument
28 nrf_vpr_clic_int_priority_set(NRF_VPRCLIC, irq, NRF_VPR_CLIC_INT_TO_PRIO(pri)); in riscv_clic_irq_priority_set()
31 void riscv_clic_irq_set_pending(uint32_t irq) in riscv_clic_irq_set_pending() argument
33 nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, irq); in riscv_clic_irq_set_pending()
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| D | intc_eirq_nxp_s32.c | 67 uint8_t irq; in eirq_nxp_s32_interrupt_handler() local
74 irq = u64_count_trailing_zeros(mask); in eirq_nxp_s32_interrupt_handler()
79 if (data->cb[irq].cb != NULL) { in eirq_nxp_s32_interrupt_handler()
80 data->cb[irq].cb(data->cb[irq].pin, data->cb[irq].data); in eirq_nxp_s32_interrupt_handler()
87 int eirq_nxp_s32_set_callback(const struct device *dev, uint8_t irq, uint8_t pin, in eirq_nxp_s32_set_callback() argument
92 __ASSERT_NO_MSG(irq < CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX); in eirq_nxp_s32_set_callback()
94 if ((data->cb[irq].cb == cb) && (data->cb[irq].data == arg)) { in eirq_nxp_s32_set_callback()
98 if (data->cb[irq].cb) { in eirq_nxp_s32_set_callback()
102 data->cb[irq].cb = cb; in eirq_nxp_s32_set_callback()
103 data->cb[irq].pin = pin; in eirq_nxp_s32_set_callback()
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| /Zephyr-latest/boards/native/native_posix/ |
| D | irq_ctrl.c | 75 void hw_irq_ctrl_prio_set(unsigned int irq, unsigned int prio) in hw_irq_ctrl_prio_set() argument
77 irq_prio[irq] = prio; in hw_irq_ctrl_prio_set()
80 uint8_t hw_irq_ctrl_get_prio(unsigned int irq) in hw_irq_ctrl_get_prio() argument
82 return irq_prio[irq]; in hw_irq_ctrl_get_prio()
151 void hw_irq_ctrl_disable_irq(unsigned int irq) in hw_irq_ctrl_disable_irq() argument
153 irq_mask &= ~((uint64_t)1<<irq); in hw_irq_ctrl_disable_irq()
156 int hw_irq_ctrl_is_irq_enabled(unsigned int irq) in hw_irq_ctrl_is_irq_enabled() argument
158 return (irq_mask & ((uint64_t)1 << irq))?1:0; in hw_irq_ctrl_is_irq_enabled()
166 void hw_irq_ctrl_clear_irq(unsigned int irq) in hw_irq_ctrl_clear_irq() argument
168 irq_status &= ~((uint64_t)1<<irq); in hw_irq_ctrl_clear_irq()
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| /Zephyr-latest/include/zephyr/arch/xtensa/ |
| D | irq.h | 87 void z_soc_irq_enable(unsigned int irq);
88 void z_soc_irq_disable(unsigned int irq);
89 int z_soc_irq_is_enabled(unsigned int irq);
91 #define arch_irq_enable(irq) z_soc_irq_enable(irq) argument
92 #define arch_irq_disable(irq) z_soc_irq_disable(irq) argument
94 #define arch_irq_is_enabled(irq) z_soc_irq_is_enabled(irq) argument
97 extern int z_soc_irq_connect_dynamic(unsigned int irq, unsigned int priority,
106 #define arch_irq_enable(irq) xtensa_irq_enable(irq) argument
107 #define arch_irq_disable(irq) xtensa_irq_disable(irq) argument
109 #define arch_irq_is_enabled(irq) xtensa_irq_is_enabled(irq) argument
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| /Zephyr-latest/soc/mediatek/mt8xxx/ |
| D | irq.c | 9 bool intc_mtk_adsp_get_enable(const struct device *dev, int irq);
10 void intc_mtk_adsp_set_enable(const struct device *dev, int irq, bool val);
44 void z_soc_irq_enable(unsigned int irq) in z_soc_irq_enable() argument
47 if (irq < 32) { in z_soc_irq_enable()
48 xtensa_irq_enable(irq); in z_soc_irq_enable()
50 const struct device *dev = irq_dev(&irq); in z_soc_irq_enable()
52 intc_mtk_adsp_set_enable(dev, irq, true); in z_soc_irq_enable()
56 void z_soc_irq_disable(unsigned int irq) in z_soc_irq_disable() argument
58 if (irq < 32) { in z_soc_irq_disable()
59 xtensa_irq_disable(irq); in z_soc_irq_disable()
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| /Zephyr-latest/include/zephyr/arch/arm64/ |
| D | irq.h | 38 extern void arch_irq_enable(unsigned int irq);
39 extern void arch_irq_disable(unsigned int irq);
40 extern int arch_irq_is_enabled(unsigned int irq);
43 extern void z_arm64_irq_priority_set(unsigned int irq, unsigned int prio,
54 void z_soc_irq_enable(unsigned int irq);
55 void z_soc_irq_disable(unsigned int irq);
56 int z_soc_irq_is_enabled(unsigned int irq);
59 unsigned int irq, unsigned int prio, unsigned int flags);
62 void z_soc_irq_eoi(unsigned int irq);
64 #define arch_irq_enable(irq) z_soc_irq_enable(irq)
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| /Zephyr-latest/dts/arm/nuvoton/npcx/ |
| D | npcx-miwus-int-map.dtsi | 15 irq = <31>;
16 irq-prio = <2>;
20 irq = <15>;
21 irq-prio = <2>;
31 irq = <47>;
32 irq-prio = <2>;
36 irq = <48>;
37 irq-prio = <2>;
41 irq = <49>;
42 irq-prio = <2>;
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| /Zephyr-latest/scripts/native_simulator/native/src/ |
| D | irq_ctrl.c | 71 void hw_irq_ctrl_prio_set(unsigned int irq, unsigned int prio) in hw_irq_ctrl_prio_set() argument
73 irq_prio[irq] = prio; in hw_irq_ctrl_prio_set()
76 uint8_t hw_irq_ctrl_get_prio(unsigned int irq) in hw_irq_ctrl_get_prio() argument
78 return irq_prio[irq]; in hw_irq_ctrl_get_prio()
152 void hw_irq_ctrl_disable_irq(unsigned int irq) in hw_irq_ctrl_disable_irq() argument
154 irq_mask &= ~((uint64_t)1<<irq); in hw_irq_ctrl_disable_irq()
157 int hw_irq_ctrl_is_irq_enabled(unsigned int irq) in hw_irq_ctrl_is_irq_enabled() argument
159 return (irq_mask & ((uint64_t)1 << irq))?1:0; in hw_irq_ctrl_is_irq_enabled()
176 void hw_irq_ctrl_clear_irq(unsigned int irq) in hw_irq_ctrl_clear_irq() argument
178 irq_status &= ~((uint64_t)1<<irq); in hw_irq_ctrl_clear_irq()
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| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | irq_manage.c | 32 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG) argument
33 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG) argument
37 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
39 NVIC_EnableIRQ((IRQn_Type)irq); in arch_irq_enable()
42 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
44 NVIC_DisableIRQ((IRQn_Type)irq); in arch_irq_disable()
47 int arch_irq_is_enabled(unsigned int irq) in arch_irq_is_enabled() argument
49 return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq)); in arch_irq_is_enabled()
61 void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_arm_irq_priority_set() argument
90 prio - _IRQ_PRIO_OFFSET, irq, in z_arm_irq_priority_set()
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| /Zephyr-latest/tests/arch/arm/arm_custom_interrupt/src/ |
| D | arm_custom_interrupt.c | 25 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG) argument
26 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG) argument
30 int irq = 0; in z_soc_irq_init() local
32 for (; irq < CONFIG_NUM_IRQS; irq++) { in z_soc_irq_init()
33 NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET); in z_soc_irq_init()
39 void z_soc_irq_enable(unsigned int irq) in z_soc_irq_enable() argument
41 if (irq == sw_irq_number) { in z_soc_irq_enable()
44 NVIC_EnableIRQ((IRQn_Type)irq); in z_soc_irq_enable()
47 void z_soc_irq_disable(unsigned int irq) in z_soc_irq_disable() argument
49 if (irq == sw_irq_number) { in z_soc_irq_disable()
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| /Zephyr-latest/arch/arm64/core/ |
| D | irq_manage.c | 35 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
37 arm_gic_irq_enable(irq); in arch_irq_enable()
40 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
42 arm_gic_irq_disable(irq); in arch_irq_disable()
45 int arch_irq_is_enabled(unsigned int irq) in arch_irq_is_enabled() argument
47 return arm_gic_irq_is_enabled(irq); in arch_irq_is_enabled()
50 void z_arm64_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_arm64_irq_priority_set() argument
52 arm_gic_irq_set_priority(irq, prio, flags); in z_arm64_irq_priority_set()
57 int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, in arch_irq_connect_dynamic() argument
61 z_isr_install(irq, routine, parameter); in arch_irq_connect_dynamic()
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| /Zephyr-latest/arch/arm/core/cortex_a_r/ |
| D | irq_manage.c | 43 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
45 arm_gic_irq_enable(irq); in arch_irq_enable()
48 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
50 arm_gic_irq_disable(irq); in arch_irq_disable()
53 int arch_irq_is_enabled(unsigned int irq) in arch_irq_is_enabled() argument
55 return arm_gic_irq_is_enabled(irq); in arch_irq_is_enabled()
68 void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_arm_irq_priority_set() argument
70 arm_gic_irq_set_priority(irq, prio, flags); in z_arm_irq_priority_set()
110 int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, in arch_irq_connect_dynamic() argument
114 z_isr_install(irq, routine, parameter); in arch_irq_connect_dynamic()
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| /Zephyr-latest/soc/ti/k3/am6x/r5/ |
| D | soc.c | 17 void z_soc_irq_eoi(unsigned int irq) in z_soc_irq_eoi() argument
19 z_vim_irq_eoi(irq); in z_soc_irq_eoi()
27 void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_soc_irq_priority_set() argument
30 z_vim_irq_priority_set(irq, prio, flags); in z_soc_irq_priority_set()
33 void z_soc_irq_enable(unsigned int irq) in z_soc_irq_enable() argument
36 z_vim_irq_enable(irq); in z_soc_irq_enable()
39 void z_soc_irq_disable(unsigned int irq) in z_soc_irq_disable() argument
42 z_vim_irq_disable(irq); in z_soc_irq_disable()
45 int z_soc_irq_is_enabled(unsigned int irq) in z_soc_irq_is_enabled() argument
48 return z_vim_irq_is_enabled(irq); in z_soc_irq_is_enabled()
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| /Zephyr-latest/include/zephyr/arch/arc/v2/ |
| D | arcv2_irq_unit.h | 50 int irq, in z_arc_v2_irq_unit_irq_enable_set() argument
56 z_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq); in z_arc_v2_irq_unit_irq_enable_set()
69 void z_arc_v2_irq_unit_int_enable(int irq) in z_arc_v2_irq_unit_int_enable() argument
71 z_arc_v2_irq_unit_irq_enable_set(irq, _ARC_V2_INT_ENABLE); in z_arc_v2_irq_unit_int_enable()
81 void z_arc_v2_irq_unit_int_disable(int irq) in z_arc_v2_irq_unit_int_disable() argument
83 z_arc_v2_irq_unit_irq_enable_set(irq, _ARC_V2_INT_DISABLE); in z_arc_v2_irq_unit_int_disable()
95 bool z_arc_v2_irq_unit_int_enabled(int irq) in z_arc_v2_irq_unit_int_enabled() argument
100 z_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq); in z_arc_v2_irq_unit_int_enabled()
116 void z_arc_v2_irq_unit_prio_set(int irq, unsigned char prio) in z_arc_v2_irq_unit_prio_set() argument
121 z_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq); in z_arc_v2_irq_unit_prio_set()
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| /Zephyr-latest/arch/posix/core/ |
| D | irq.c | 23 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
25 posix_irq_enable(irq); in arch_irq_enable()
28 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
30 posix_irq_disable(irq); in arch_irq_disable()
33 int arch_irq_is_enabled(unsigned int irq) in arch_irq_is_enabled() argument
35 return posix_irq_is_enabled(irq); in arch_irq_is_enabled()
52 int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, in arch_irq_connect_dynamic() argument
56 posix_isr_declare(irq, (int)flags, routine, parameter); in arch_irq_connect_dynamic()
57 posix_irq_priority_set(irq, priority, flags); in arch_irq_connect_dynamic()
58 return irq; in arch_irq_connect_dynamic()
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| /Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/ |
| D | npcx4-miwus-int-map.dtsi | 19 irq = <7>;
20 irq-prio = <2>;
24 irq = <5>;
25 irq-prio = <2>;
29 irq = <11>;
30 irq-prio = <2>;
34 irq = <35>;
35 irq-prio = <2>;
39 irq = <42>;
40 irq-prio = <2>;
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