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Searched refs:SDMMC2_SEL (Results 1 – 5 of 5) sorted by relevance

/Zephyr-latest/dts/arm/st/h5/
Dstm32h563.dtsi17 <&rcc STM32_SRC_PLL1_Q SDMMC2_SEL(0)>;
/Zephyr-latest/dts/arm/st/f7/
Dstm32f722.dtsi39 <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
Dstm32f765.dtsi88 <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32f7_clock.h118 #define SDMMC2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR2_REG) macro
Dstm32h5_clock.h133 #define SDMMC2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 7, CCIPR4_REG) macro