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Searched refs:SDMMC1_SEL (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32f7_clock.h117 #define SDMMC1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG) macro
Dstm32h5_clock.h132 #define SDMMC1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CCIPR4_REG) macro
/Zephyr-latest/dts/arm/st/h5/
Dstm32h562.dtsi483 <&rcc STM32_SRC_PLL1_Q SDMMC1_SEL(0)>;
/Zephyr-latest/dts/arm/st/f7/
Dstm32f7.dtsi843 <&rcc STM32_SRC_PLL_Q SDMMC1_SEL(0)>;