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Searched refs:FIELD_PREP (Results 1 – 25 of 93) sorted by relevance

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/Zephyr-latest/include/zephyr/dt-bindings/clock/silabs/
Dxg23-clock.h24 #define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18))
25 #define CLOCK_ACMP1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19))
26 #define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0))
27 #define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11))
28 #define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11))
29 #define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28))
30 #define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29))
31 #define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31))
32 #define CLOCK_DMEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 27))
33 #define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17))
[all …]
Dxg24-clock.h24 #define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18))
25 #define CLOCK_ACMP1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19))
26 #define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0))
27 #define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11))
28 #define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11))
29 #define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28))
30 #define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29))
31 #define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31))
32 #define CLOCK_DMEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 27))
33 #define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17))
[all …]
Dxg22-clock.h24 #define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0))
25 #define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11))
26 #define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11))
27 #define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28))
28 #define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29))
29 #define CLOCK_CRYPTOACC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13))
30 #define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31))
31 #define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17))
32 #define CLOCK_EUART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 24))
33 #define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3))
[all …]
Dxg27-clock.h24 #define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19))
25 #define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0))
26 #define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11))
27 #define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11))
28 #define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28))
29 #define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29))
30 #define CLOCK_CRYPTOACC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13))
31 #define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31))
32 #define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17))
33 #define CLOCK_ETAMPDET (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28))
[all …]
/Zephyr-latest/drivers/can/
Dcan_sja1000_priv.h98 #define CAN_SJA1000_BTR0_BRP_PREP(brp) FIELD_PREP(CAN_SJA1000_BTR0_BRP_MASK, brp)
99 #define CAN_SJA1000_BTR0_SJW_PREP(sjw) FIELD_PREP(CAN_SJA1000_BTR0_SJW_MASK, sjw)
106 #define CAN_SJA1000_BTR1_TSEG1_PREP(tseg1) FIELD_PREP(CAN_SJA1000_BTR1_TSEG1_MASK, tseg1)
107 #define CAN_SJA1000_BTR1_TSEG2_PREP(tseg2) FIELD_PREP(CAN_SJA1000_BTR1_TSEG2_MASK, tseg2)
114 #define CAN_SJA1000_ECC_SEG_SOF FIELD_PREP(CAN_SJA1000_ECC_SEG_MASK, 3U)
115 #define CAN_SJA1000_ECC_SEG_ID28_TO_ID21 FIELD_PREP(CAN_SJA1000_ECC_SEG_MASK, 2U)
116 #define CAN_SJA1000_ECC_SEG_ID20_TO_ID18 FIELD_PREP(CAN_SJA1000_ECC_SEG_MASK, 6U)
117 #define CAN_SJA1000_ECC_SEG_SRTR FIELD_PREP(CAN_SJA1000_ECC_SEG_MASK, 4U)
118 #define CAN_SJA1000_ECC_SEG_IDE FIELD_PREP(CAN_SJA1000_ECC_SEG_MASK, 5U)
119 #define CAN_SJA1000_ECC_SEG_ID17_TO_ID13 FIELD_PREP(CAN_SJA1000_ECC_SEG_MASK, 7U)
[all …]
/Zephyr-latest/soc/nxp/s32/s32k3/
Dpmc.c15 #define PMC_LVSC_HVDAF(v) FIELD_PREP(PMC_LVSC_HVDAF_MASK, (v))
17 #define PMC_LVSC_HVDBF(v) FIELD_PREP(PMC_LVSC_HVDBF_MASK, (v))
19 #define PMC_LVSC_HVD25F(v) FIELD_PREP(PMC_LVSC_HVD25F_MASK, (v))
21 #define PMC_LVSC_HVD11F(v) FIELD_PREP(PMC_LVSC_HVD11F_MASK, (v))
23 #define PMC_LVSC_LVD5AF(v) FIELD_PREP(PMC_LVSC_LVD5AF_MASK, (v))
25 #define PMC_LVSC_LVD15F(v) FIELD_PREP(PMC_LVSC_LVD15F_MASK, (v))
27 #define PMC_LVSC_HVDAS(v) FIELD_PREP(PMC_LVSC_HVDAS_MASK, (v))
29 #define PMC_LVSC_HVDBS(v) FIELD_PREP(PMC_LVSC_HVDBS_MASK, (v))
31 #define PMC_LVSC_HVD25S(v) FIELD_PREP(PMC_LVSC_HVD25S_MASK, (v))
33 #define PMC_LVSC_HVD11S(v) FIELD_PREP(PMC_LVSC_HVD11S_MASK, (v))
[all …]
Dpinctrl_soc.h17 #define SIUL2_MSCR_SSS(v) FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v))
19 #define SIUL2_MSCR_SMC(v) FIELD_PREP(SIUL2_MSCR_SMC_MASK, (v))
21 #define SIUL2_MSCR_IFE(v) FIELD_PREP(SIUL2_MSCR_IFE_MASK, (v))
23 #define SIUL2_MSCR_DSE(v) FIELD_PREP(SIUL2_MSCR_DSE_MASK, (v))
25 #define SIUL2_MSCR_PUS(v) FIELD_PREP(SIUL2_MSCR_PUS_MASK, (v))
27 #define SIUL2_MSCR_PUE(v) FIELD_PREP(SIUL2_MSCR_PUE_MASK, (v))
29 #define SIUL2_MSCR_SRC(v) FIELD_PREP(SIUL2_MSCR_SRC_MASK, (v))
31 #define SIUL2_MSCR_PKE(v) FIELD_PREP(SIUL2_MSCR_PKE_MASK, (v))
33 #define SIUL2_MSCR_INV(v) FIELD_PREP(SIUL2_MSCR_INV_MASK, (v))
35 #define SIUL2_MSCR_IBE(v) FIELD_PREP(SIUL2_MSCR_IBE_MASK, (v))
[all …]
/Zephyr-latest/soc/nxp/s32/s32ze/
Dpinctrl_soc.h17 #define SIUL2_MSCR_SSS(v) FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v))
19 #define SIUL2_MSCR_SMC(v) FIELD_PREP(SIUL2_MSCR_SMC_MASK, (v))
21 #define SIUL2_MSCR_TRC(v) FIELD_PREP(SIUL2_MSCR_TRC_MASK, (v))
23 #define SIUL2_MSCR_RCVR(v) FIELD_PREP(SIUL2_MSCR_RCVR_MASK, (v))
25 #define SIUL2_MSCR_CREF(v) FIELD_PREP(SIUL2_MSCR_CREF_MASK, (v))
27 #define SIUL2_MSCR_PUS(v) FIELD_PREP(SIUL2_MSCR_PUS_MASK, (v))
29 #define SIUL2_MSCR_PUE(v) FIELD_PREP(SIUL2_MSCR_PUE_MASK, (v))
31 #define SIUL2_MSCR_SRE(v) FIELD_PREP(SIUL2_MSCR_SRE_MASK, (v))
33 #define SIUL2_MSCR_RXCB(v) FIELD_PREP(SIUL2_MSCR_RXCB_MASK, (v))
35 #define SIUL2_MSCR_IBE(v) FIELD_PREP(SIUL2_MSCR_IBE_MASK, (v))
[all …]
/Zephyr-latest/soc/nxp/s32/common/
Dmc_me.c17 #define MC_ME_CTL_KEY_KEY(v) FIELD_PREP(MC_ME_CTL_KEY_KEY_MASK, (v))
21 #define MC_ME_MODE_CONF_DEST_RST(v) FIELD_PREP(MC_ME_MODE_CONF_DEST_RST_MASK, (v))
23 #define MC_ME_MODE_CONF_FUNC_RST(v) FIELD_PREP(MC_ME_MODE_CONF_FUNC_RST_MASK, (v))
25 #define MC_ME_MODE_CONF_STANDBY(v) FIELD_PREP(MC_ME_MODE_CONF_STANDBY_MASK, (v))
29 #define MC_ME_MODE_UPD_MODE_UPD(v) FIELD_PREP(MC_ME_MODE_UPD_MODE_UPD_MASK, (v))
33 #define MC_ME_MODE_STAT_PREV_MODE(v) FIELD_PREP(MC_ME_MODE_STAT_PREV_MODE_MASK, (v))
37 #define MC_ME_MAIN_COREID_CIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_CIDX_MASK, (v))
39 #define MC_ME_MAIN_COREID_PIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_PIDX_MASK, (v))
43 #define MC_ME_PRTN_PCONF_PCE(v) FIELD_PREP(MC_ME_PRTN_PCONF_PCE_MASK, (v))
47 #define MC_ME_PRTN_PUPD_PCUD(v) FIELD_PREP(MC_ME_PRTN_PUPD_PCUD_MASK, (v))
[all …]
Dmc_rgm.c15 #define MC_RGM_DES_F_POR(v) FIELD_PREP(MC_RGM_DES_F_POR_MASK, (v))
19 #define MC_RGM_FES_F_EXR(v) FIELD_PREP(MC_RGM_FES_F_EXR_MASK, (v))
27 #define MC_RGM_FREC_FREC(v) FIELD_PREP(MC_RGM_FREC_FREC_MASK, (v))
31 #define MC_RGM_FRET_FRET(v) FIELD_PREP(MC_RGM_FRET_FRET_MASK, (v))
35 #define MC_RGM_DRET_DRET(v) FIELD_PREP(MC_RGM_DRET_DRET_MASK, (v))
39 #define MC_RGM_ERCTRL_ERASSERT(v) FIELD_PREP(MC_RGM_ERCTRL_ERASSERT_MASK, (v))
43 #define MC_RGM_RDSS_DES_RES(v) FIELD_PREP(MC_RGM_RDSS_DES_RES_MASK, (v))
45 #define MC_RGM_RDSS_FES_RES(v) FIELD_PREP(MC_RGM_RDSS_FES_RES_MASK, (v))
49 #define MC_RGM_FRENTC_FRET_EN(v) FIELD_PREP(MC_RGM_FRENTC_FRET_EN_MASK, (v))
51 #define MC_RGM_FRENTC_FRET_TIMEOUT(v) FIELD_PREP(MC_RGM_FRENTC_FRET_TIMEOUT_MASK, (v))
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dsilabs-pinctrl-dbus.h33 (FIELD_PREP(SILABS_PINCTRL_GPIO_PORT_MASK, port) | \
34 FIELD_PREP(SILABS_PINCTRL_GPIO_PIN_MASK, pin) | \
35 FIELD_PREP(SILABS_PINCTRL_PERIPH_BASE_MASK, periph_base) | \
36 FIELD_PREP(SILABS_PINCTRL_HAVE_EN_MASK, en_present) | \
37 FIELD_PREP(SILABS_PINCTRL_EN_BIT_MASK, en_bit) | \
38 FIELD_PREP(SILABS_PINCTRL_ROUTE_MASK, route))
/Zephyr-latest/drivers/flash/
Dflash_cadence_nand_ll.h127 #define CNF_ASYNC_TIMINGS_TRH FIELD_PREP(GENMASK(28, 24), 2)
128 #define CNF_ASYNC_TIMINGS_TRP FIELD_PREP(GENMASK(20, 16), 4)
129 #define CNF_ASYNC_TIMINGS_TWH FIELD_PREP(GENMASK(12, 8), 2)
130 #define CNF_ASYNC_TIMINGS_TWP FIELD_PREP(GENMASK(4, 0), 4)
154 #define CDMA_CF_DMA_MASTER_SET(x) FIELD_PREP(BIT(CDMA_CF_DMA_MASTER), x)
156 #define F_CFLAGS_VOL_ID_SET(x) FIELD_PREP(GENMASK(7, 4), x)
164 #define CFLAGS_MPTRPC_SET FIELD_PREP(BIT(CFLAGS_MPTRPC), 1)
166 #define CFLAGS_FPTRPC_SET FIELD_PREP(BIT(CFLAGS_FPTRPC), 1)
168 #define CFLAGS_CONT_SET FIELD_PREP(BIT(CFLAGS_CONT), 1)
193 #define CMD_0_THREAD_POS_SET(x) (FIELD_PREP(GENMASK(26, 24), x))
[all …]
/Zephyr-latest/include/zephyr/drivers/can/
Dcan_sja1000.h30 #define CAN_SJA1000_OCR_OCMODE_BIPHASE FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 0U)
31 #define CAN_SJA1000_OCR_OCMODE_TEST FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 1U)
32 #define CAN_SJA1000_OCR_OCMODE_NORMAL FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 2U)
33 #define CAN_SJA1000_OCR_OCMODE_CLOCK FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 3U)
48 #define CAN_SJA1000_CDR_CD_DIV1 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 7U)
49 #define CAN_SJA1000_CDR_CD_DIV2 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 0U)
50 #define CAN_SJA1000_CDR_CD_DIV4 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 1U)
51 #define CAN_SJA1000_CDR_CD_DIV6 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 2U)
52 #define CAN_SJA1000_CDR_CD_DIV8 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 3U)
53 #define CAN_SJA1000_CDR_CD_DIV10 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 4U)
[all …]
/Zephyr-latest/drivers/ethernet/
Doa_tc6.c39 *hdr = FIELD_PREP(OA_CTRL_HDR_DNC, 0) | in oa_tc6_reg_read()
40 FIELD_PREP(OA_CTRL_HDR_WNR, 0) | in oa_tc6_reg_read()
41 FIELD_PREP(OA_CTRL_HDR_AID, 0) | in oa_tc6_reg_read()
42 FIELD_PREP(OA_CTRL_HDR_MMS, reg >> 16) | in oa_tc6_reg_read()
43 FIELD_PREP(OA_CTRL_HDR_ADDR, reg) | in oa_tc6_reg_read()
44 FIELD_PREP(OA_CTRL_HDR_LEN, 0); /* To read single register len = 0 */ in oa_tc6_reg_read()
45 *hdr |= FIELD_PREP(OA_CTRL_HDR_P, oa_tc6_get_parity(*hdr)); in oa_tc6_reg_read()
97 *hdr = FIELD_PREP(OA_CTRL_HDR_DNC, 0) | in oa_tc6_reg_write()
98 FIELD_PREP(OA_CTRL_HDR_WNR, 1) | in oa_tc6_reg_write()
99 FIELD_PREP(OA_CTRL_HDR_AID, 0) | in oa_tc6_reg_write()
[all …]
/Zephyr-latest/include/zephyr/bluetooth/classic/
Da2dp_codec_sbc.h89 hdr = ((hdr) & ~GENMASK(3, 0)) | FIELD_PREP(GENMASK(3, 0), (val))
92 hdr = ((hdr) & ~BIT(5)) | FIELD_PREP(BIT(5), (val))
95 hdr = ((hdr) & ~BIT(6)) | FIELD_PREP(BIT(6), (val))
98 hdr = ((hdr) & ~BIT(7)) | FIELD_PREP(BIT(7), (val))
101 FIELD_PREP(GENMASK(3, 0), num_frames) | FIELD_PREP(BIT(5), l) |\
102 FIELD_PREP(BIT(6), s) | FIELD_PREP(BIT(7), f)
/Zephyr-latest/drivers/sensor/tdk/icm42688/
Dicm42688_common.c133 FIELD_PREP(MASK_FIFO_MODE, BIT_FIFO_MODE_BYPASS)); in icm42688_configure()
141 FIELD_PREP(BIT_FIFO_FLUSH, 1)); in icm42688_configure()
152 uint8_t pwr_mgmt0 = FIELD_PREP(MASK_GYRO_MODE, cfg->gyro_pwr_mode) | in icm42688_configure()
153 FIELD_PREP(MASK_ACCEL_MODE, cfg->accel_pwr_mode) | in icm42688_configure()
154 FIELD_PREP(BIT_TEMP_DIS, cfg->temp_dis); in icm42688_configure()
169 uint8_t accel_config0 = FIELD_PREP(MASK_ACCEL_ODR, cfg->accel_odr) | in icm42688_configure()
170 FIELD_PREP(MASK_ACCEL_UI_FS_SEL, cfg->accel_fs); in icm42688_configure()
179 uint8_t gyro_config0 = FIELD_PREP(MASK_GYRO_ODR, cfg->gyro_odr) | in icm42688_configure()
180 FIELD_PREP(MASK_GYRO_UI_FS_SEL, cfg->gyro_fs); in icm42688_configure()
196 uint8_t fifo_config_bypass = FIELD_PREP(MASK_FIFO_MODE, BIT_FIFO_MODE_BYPASS); in icm42688_configure()
[all …]
/Zephyr-latest/drivers/dai/intel/dmic/
Ddmic_nhlt.c288 val |= FIELD_PREP(DMICLVSCTL_MLCS, source); in dai_dmic_clock_select_set()
293 val |= FIELD_PREP(DMICLCTL_MLCS, source); in dai_dmic_clock_select_set()
461 ref = FIELD_PREP(OUTCONTROL_TIE, bf1) | FIELD_PREP(OUTCONTROL_SIP, bf2) | in print_outcontrol()
462 FIELD_PREP(OUTCONTROL_FINIT, bf3) | FIELD_PREP(OUTCONTROL_FCI, bf4) | in print_outcontrol()
463 FIELD_PREP(OUTCONTROL_BFTH, bf5) | FIELD_PREP(OUTCONTROL_OF, bf6) | in print_outcontrol()
464 FIELD_PREP(OUTCONTROL_IPM, bf7) | FIELD_PREP(OUTCONTROL_IPM_SOURCE_1, bf9) | in print_outcontrol()
465 FIELD_PREP(OUTCONTROL_IPM_SOURCE_2, bf10) | in print_outcontrol()
466 FIELD_PREP(OUTCONTROL_IPM_SOURCE_3, bf11) | in print_outcontrol()
467 FIELD_PREP(OUTCONTROL_IPM_SOURCE_4, bf12) | FIELD_PREP(OUTCONTROL_TH, bf8) | in print_outcontrol()
468 FIELD_PREP(OUTCONTROL_IPM_SOURCE_MODE, bf13); in print_outcontrol()
[all …]
/Zephyr-latest/drivers/watchdog/
Dwdt_nxp_s32.c22 #define SWT_CR_WEN(v) FIELD_PREP(SWT_CR_WEN_MASK, (v))
24 #define SWT_CR_FRZ(v) FIELD_PREP(SWT_CR_FRZ_MASK, (v))
26 #define SWT_CR_STP(v) FIELD_PREP(SWT_CR_STP_MASK, (v))
28 #define SWT_CR_SLK(v) FIELD_PREP(SWT_CR_SLK_MASK, (v))
30 #define SWT_CR_HLK(v) FIELD_PREP(SWT_CR_HLK_MASK, (v))
32 #define SWT_CR_ITR(v) FIELD_PREP(SWT_CR_ITR_MASK, (v))
34 #define SWT_CR_WND(v) FIELD_PREP(SWT_CR_WND_MASK, (v))
36 #define SWT_CR_RIA(v) FIELD_PREP(SWT_CR_RIA_MASK, (v))
38 #define SWT_CR_SMD(v) FIELD_PREP(SWT_CR_SMD_MASK, (v))
40 #define SWT_CR_MAP(v) FIELD_PREP(SWT_CR_MAP_MASK, (v))
[all …]
/Zephyr-latest/include/zephyr/sensing/
Dsensing.h56 (FIELD_PREP(GENMASK(31, 24), _major) | \
57 FIELD_PREP(GENMASK(23, 16), _minor) | \
58 FIELD_PREP(GENMASK(15, 8), _hotfix) | \
59 FIELD_PREP(GENMASK(7, 0), _build))
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dcomm_widget.h776 uint32_t attr = FIELD_PREP(USATTR_DSTPID, dest) | FIELD_PREP(USATTR_FID, func) | in cw_upstream_set_attr()
777 FIELD_PREP(USATTR_OPC, opcode) | FIELD_PREP(USATTR_BE, be) | in cw_upstream_set_attr()
778 FIELD_PREP(USATTR_BAR, bar); in cw_upstream_set_attr()
829 cmd |= FIELD_PREP(USCMD_MSGTYP, CW_TRANSACTION_POSTED) | in cw_upstream_do_pw()
830 FIELD_PREP(USCMD_TRANTYP, CW_TRANSACTION_WRITE) | in cw_upstream_do_pw()
Dcomm_widget_messages.c23 uint32_t iface = FIELD_PREP(CW_PMC_IPC_OP_CODE, CW_PMC_OPC_SRAM_CONFIG) | in adsp_comm_widget_pmc_send_ipc()
24 FIELD_PREP(CW_PMC_IPC_SRAM_USED_BANKS, banks) | in adsp_comm_widget_pmc_send_ipc()
/Zephyr-latest/drivers/counter/
Dcounter_ace_v1x_art.c23 val |= FIELD_PREP(ACE_TSCTRL_IONTE_MASK, new_timestamp_enable); in counter_ace_v1x_art_ionte_set()
33 val |= FIELD_PREP(ACE_TSCTRL_CDMAS_MASK, cdmas); in counter_ace_v1x_art_cdmas_set()
43 val |= FIELD_PREP(ACE_TSCTRL_NTK_MASK, new_timestamp_taken); in counter_ace_v1x_art_ntk_set()
58 val |= FIELD_PREP(ACE_TSCTRL_HHTSE_MASK, enable); in counter_ace_v1x_art_hhtse_set()
/Zephyr-latest/drivers/sensor/adi/adxl367/
Dadxl367.c46 FIELD_PREP(ADXL367_ACT_INACT_CTL_ACT_EN_MSK, th->enable) | in adxl367_setup_activity_detection()
47 FIELD_PREP(ADXL367_ACT_INACT_CTL_ACT_REF_MSK, in adxl367_setup_activity_detection()
54 FIELD_PREP(ADXL367_THRESH_H_MSK, th->value >> 6)); in adxl367_setup_activity_detection()
60 FIELD_PREP(ADXL367_THRESH_L_MSK, th->value & 0x3F)); in adxl367_setup_activity_detection()
83 FIELD_PREP(ADXL367_ACT_INACT_CTL_INACT_EN_MSK, in adxl367_setup_inactivity_detection()
85 FIELD_PREP(ADXL367_ACT_INACT_CTL_INACT_REF_MSK, in adxl367_setup_inactivity_detection()
92 FIELD_PREP(ADXL367_THRESH_H_MSK, th->value >> 6)); in adxl367_setup_inactivity_detection()
98 FIELD_PREP(ADXL367_THRESH_L_MSK, th->value & 0x3F)); in adxl367_setup_inactivity_detection()
124 FIELD_PREP(ADXL367_POWER_CTL_MEASURE_MSK, op_mode)); in adxl367_set_op_mode()
136 data->pwr_reg |= FIELD_PREP(ADXL367_POWER_CTL_MEASURE_MSK, op_mode); in adxl367_set_op_mode()
[all …]
/Zephyr-latest/subsys/bluetooth/host/classic/
Davctp_internal.h58 (hdr)->byte0 = (((hdr)->byte0) & ~GENMASK(7, 4)) | FIELD_PREP(GENMASK(7, 4), (tl))
63 (hdr)->byte0 = (((hdr)->byte0) & ~GENMASK(3, 2)) | FIELD_PREP(GENMASK(3, 2), (packet_type))
66 (hdr)->byte0 = (((hdr)->byte0) & ~BIT(1)) | FIELD_PREP(BIT(1), (cr))
72 (hdr)->byte0 = (((hdr)->byte0) & ~BIT(0)) | FIELD_PREP(BIT(0), (ipid))
/Zephyr-latest/drivers/led_strip/
Dtlc5971.c101 return FIELD_PREP(TLC5971_BYTE27_WRITE_CMD_MASK, TLC5971_WRITE_COMMAND) | in tlc5971_data_byte27()
102 FIELD_PREP(TLC5971_BYTE27_CTRL_MASK, control_data); in tlc5971_data_byte27()
114 return FIELD_PREP(TLC5971_BYTE26_CTRL_MASK, control_data) | in tlc5971_data_byte26()
115 FIELD_PREP(TLC5971_BYTE26_GBC1_MASK, (gbc_color_1 >> 2)); in tlc5971_data_byte26()
127 return FIELD_PREP(TLC5971_BYTE25_GBC1_MASK, gbc_color_1) | in tlc5971_data_byte25()
128 FIELD_PREP(TLC5971_BYTE25_GBC2_MASK, (gbc_color_2 >> 1)); in tlc5971_data_byte25()
140 return FIELD_PREP(TLC5971_BYTE24_GBC2_MASK, gbc_color_2) | in tlc5971_data_byte24()
141 FIELD_PREP(TLC5971_BYTE24_GBC3_MASK, gbc_color_3); in tlc5971_data_byte24()

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