Searched refs:CFGR3_REG (Results 1 – 2 of 2) sorted by relevance
| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32f3_clock.h | 64 #define CFGR3_REG 0x30 macro
75 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)
76 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)
77 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 5, CFGR3_REG)
78 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)
79 #define TIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, CFGR3_REG)
80 #define TIM8_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 9, CFGR3_REG)
81 #define TIM15_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 10, CFGR3_REG)
82 #define TIM16_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 11, CFGR3_REG)
83 #define TIM17_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 13, CFGR3_REG)
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| D | stm32f0_clock.h | 63 #define CFGR3_REG 0x30 macro
70 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)
71 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)
72 #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)
73 #define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 7, CFGR3_REG)
74 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG)
75 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG)
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