Home
last modified time | relevance | path

Searched refs:RESET_SW (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/soc/mediatek/mt8xxx/
Dmtk_adsp_load.py80 r.RESET_SW = 0x0024 # Xtensa halt/reset/boot control
91 self.cfg.RESET_SW |= 8 # Set RUNSTALL: halt CPU
92 self.cfg.RESET_SW |= 3 # Set low two bits: "BRESET|DRESET"
96 self.cfg.RESET_SW |= 0x10 # Enable "alternate reset" boot vector
98 self.cfg.RESET_SW &= ~3 # Release reset bits
99 self.cfg.RESET_SW &= ~8 # Clear RUNSTALL: go!
/Zephyr-latest/drivers/led/
Dlp50xx.c76 #define RESET_SW 0xFF macro
214 buf[1] = RESET_SW; in lp50xx_reset()