Searched refs:with (Results 176 – 200 of 2945) sorted by relevance
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| /Zephyr-latest/cmake/toolchain/llvm/ |
| D | Kconfig | 12 Use binutils ld linker with llvm/clang.
17 Use LLVM built-in lld linker with llvm/clang.
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| /Zephyr-latest/boards/st/nucleo_h745zi_q/doc/ |
| D | index.rst | 14 open development platform with a wide choice of specialized shields.
18 The STM32 Nucleo-144 board comes with the STM32 comprehensive free software
19 libraries and examples available with the STM32Cube MCU Package.
24 - Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
31 - USB with Micro-AB
38 - On-board ST-LINK/V3 debugger/programmer with USB re-enumeration
41 - Comprehensive free software libraries and examples available with the
53 - ARM 32-bit Cortex-M7 CPU with FPU
54 - ARM 32-bit Cortex-M4 CPU with FPU
77 - GPIO (up to 114) with external interrupt capability
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| /Zephyr-latest/boards/snps/nsim/arc_classic/doc/ |
| D | index.rst | 7 simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The
22 * ``nsim/nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and
24 * ``nsim/nsim_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's
25 * ``nsim/nsim_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options a…
27 * ``nsim/nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4
28 * ``nsim/nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
29 * ``nsim/nsim_hs/smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
31 * ``nsim/nsim_hs5x`` - 32-bit ARCv3 HS core with rich set of options
32 * ``nsim/nsim_hs6x`` - 64-bit ARCv3 HS core with rich set of options
44 Note that these files contain identical HW configuration and meant to be used with the corresponding
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| /Zephyr-latest/arch/arm/core/ |
| D | Kconfig.vfp | 7 # indicate that the CPU core can be configured with the specified
35 that supports only single-precision operations with 16 double-word
46 that supports half- and single-precision operations with 16
59 multiply-accumulate) with 16 double-word registers.
69 that supports single- and double-precision operations with 16
81 that supports half-, single- and double-precision operations with 16
95 (including fused multiply-accumulate) with 16 double-word registers.
109 fused multiply-accumulate) and floating-point exception trapping with 16
123 (including fused multiply-accumulate) with 32 double-word registers.
137 fused multiply-accumulate) and floating-point exception trapping with 32
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| /Zephyr-latest/boards/st/stm32f413h_disco/doc/ |
| D | index.rst | 7 with a wide range of connectivity support and configurations. Here are
18 - 1.54 inch 240x240 pixel TFT color LCD with parallel interface and capacitive touchscreen
19 - I2S Audio CODEC, with a stereo headset jack, including analog microphone input and a loudspeaker …
27 - USB OTG FS with Micro-AB connector
36 - Compatible with Arduino(tm) Uno revision 3 connectors
48 - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU
53 - GPIO with external interrupt capability
55 - 1x12-bit ADC with 16 channels
136 the USB port, then run a serial host program to connect with your
174 …https://www.st.com/resource/en/user_manual/um2135-discovery-kit-with-stm32f413zh-mcu-stmicroelectr…
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| /Zephyr-latest/boards/st/nucleo_g0b1re/doc/ |
| D | index.rst | 6 with a wide range of connectivity support and configurations. Here are
15 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector
44 - Calendar RTC with alarm and periodic wakeup
48 - 32 Mbit/s SPI(3) multiplexed with I2S(2)
53 - GPIO (up to 94) with external interrupt capability
55 - 12-bit ADC with 16 channels
56 - 12-bit DAC with 2 channels(2)
76 input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the
77 GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
125 which can be installed by adding "pack" support with the following pyocd command:
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| /Zephyr-latest/boards/st/nucleo_c031c6/doc/ |
| D | index.rst | 5 The STM32 Nucleo-64 development board with STM32C031C6 MCU, supports Arduino and ST morpho connecti…
8 and build prototypes with the STM32 microcontroller, choosing from the various
13 The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together
14 with various packaged software examples.
28 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
60 input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the
61 GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
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| /Zephyr-latest/boards/arm/fvp_baser_aemv8r/doc/ |
| D | aarch64.rst | 9 debug-with-arm-ds.rst
54 When FVP is launched with ``-a, --application FILE`` option, the kernel will be
69 This board configuration uses a single serial communication channel with the
89 Arm FVP emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
97 This will build an image with the synchronization sample app.
98 Then you can run it with ``west build -t run``.
104 See :ref:`debug_with_arm_ds` for how to debug with Arm Development Studio [5]_.
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| /Zephyr-latest/boards/others/stm32f401_mini/doc/ |
| D | index.rst | 8 More info about the board with schematics available `here <stm32-base-board-page_>`_
17 - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU
22 - GPIO with external interrupt capability
23 - 1x12-bit, 2.4 MSPS ADC with 16 channels
30 - USB 2.0 full-speed device/host/OTG controller with on-chip PHY
80 right USB drivers with a tool like `Zadig`_.
86 by setting the BOOT0 dip switch position to ON. Reset the board with the NRST button.
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| /Zephyr-latest/boards/nxp/imx91_evk/doc/ |
| D | index.rst | 9 with a small and low-cost package. The board can be used by developers
10 to get familiar with the processor before investing a large amount of
33 - ENET: 10/100/1000 Mbit/s RGMII Ethernet connected with external PHY
36 with external PHY RTL8211
83 This board configuration uses a single serial communication channel with the
102 for example, with the :zephyr:code-sample:`synchronization` sample:
110 This will build an image with the synchronization sample app, boot it and
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| /Zephyr-latest/drivers/eeprom/ |
| D | Kconfig | 29 Enable the EEPROM shell with EEPROM related commands.
55 bool "I2C EEPROMs compatible with Atmel's AT24 family"
61 Enable support for I2C EEPROMs compatible with Atmel's AT24 family.
63 There are multiple vendors manufacturing I2C EEPROMs compatible with
71 bool "SPI EEPROMs compatibile with Atmel's AT25 family"
77 Enable support for SPI EEPROMs compatible with Atmel's AT25 family.
79 There are multiple vendors manufacturing SPI EEPROMs compatible with
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| /Zephyr-latest/scripts/coccinelle/ |
| D | ztest_strcmp.cocci | 12 // Comparing result of strcmp with 0
32 // Using assert_true with !strcmp
43 // using zassert_true with strcmp(E1, E2) == 0
63 // using zassert_true with 0 == strcmp(E1, E2)
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| /Zephyr-latest/doc/services/modbus/ |
| D | index.rst | 9 with different physical interfaces, like RS485 or RS232.
14 Only one client may be present on the bus. Client can communicate with several
29 the possibility to try out RTU server and RTU client implementation with an evaluation board.
32 gateway with Zephyr OS.
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| /Zephyr-latest/samples/subsys/demand_paging/ |
| D | README.rst | 5 Leverage demand paging to deal with code bigger than available RAM.
10 This sample demonstrates how demand paging can be leveraged to deal with
19 store implementation with access to the compiled Zephyr binary.
21 a QEMU ARM64 target with a hardcoded small RAM configuration.
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| /Zephyr-latest/boards/st/stm32h7b3i_dk/doc/ |
| D | index.rst | 16 USB OTG_HS, microSD, USART, FDCAN, audio DAC stereo with audio jack input and output,
17 camera, SDRAM, Octo-SPI Flash memory and RGB interface LCD with capacitive touch
24 - 4.3" (480x272 pixels) TFT color LCD module including a capacitive touch panel with RGB interface
25 - Wi-Fi |reg| module compliant with 802.11 b/g/n
36 - USB with Micro-AB
48 - On-board STLINK-V3E debugger/programmer with USB re-enumeration capability
58 - ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU
75 - Octo-SPI memory interfaces with on-the-fly decryption(2)
78 - GPIO (up to 168) with external interrupt capability
79 - 16-bit ADC(2) with 24 channels / 3.6 MSPS
[all …]
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| /Zephyr-latest/boards/st/nucleo_h755zi_q/doc/ |
| D | index.rst | 12 open development platform with a wide choice of specialized shields.
19 - Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
26 - USB with Micro-AB
33 - On-board ST-LINK/V3 debugger/programmer with USB re-enumeration
45 - ARM 32-bit Cortex-M7 CPU with FPU
46 - ARM 32-bit Cortex-M4 CPU with FPU
69 - GPIO (up to 114) with external interrupt capability
70 - 16-bit ADC(3) with 36 channels / 3.6 MSPS
71 - 12-bit DAC with 2 channels(2)
74 - LCD-TFT Controller with XGA resolution
[all …]
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| /Zephyr-latest/boards/st/nucleo_f091rc/doc/ |
| D | index.rst | 5 The STM32 Nucleo-64 development board with STM32F091RC MCU, supports Arduino and ST morpho connecti…
8 and build prototypes with the STM32 microcontroller, choosing from the various
12 expansion of the STM32 Nucleo open development platform with a wide choice of
17 The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together
18 with various packaged software examples.
32 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
66 input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the
67 GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
89 - PWM_2_CH1 : PA5 (might conflict with SPI1)
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| /Zephyr-latest/boards/adi/sdp_k1/doc/ |
| D | index.rst | 11 - USB 2.0 device with USB-C connector
32 - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU
37 - GPIO with external interrupt capability
41 - 3x12-bit ADC with 24 channels
53 - USB 2.0 OTG FS with on-chip PHY
54 - USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI
55 - 10/100 Ethernet MAC with dedicated DMA
132 Flashing an application with a STLINK debugger
139 Run a serial host program to connect with your board:
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| /Zephyr-latest/samples/drivers/clock_control_litex/ |
| D | README.rst | 11 The driver uses Mixed Mode Clock Manager (MMCM) module to generate up to 7 clocks with defined phas…
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
41 This configuration defines 2 clock outputs: ``clk0`` and ``clk1`` with default frequency set to 100…
48 The driver is interfaced with the :ref:`Clock Control API <clock_control_api>` function ``clock_con…
50 …struct:`litex_clk_setup` onto :c:type:`clock_control_subsys_t` and use it with :c:func:`clock_cont…
70 …ase offset) can be acquired with function ``clock_control_get_status()`` and clock output frequenc…
91 Code is performed on 2 clock outputs with ``clkout_nr`` defined in ``LITEX_CLK_TEST_CLK1`` and ``LI…
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| /Zephyr-latest/samples/boards/nordic/mesh/onoff_level_lighting_vnd_app/ |
| D | README.rst | 5 Setup a Bluetooth Mesh node with various models (generic OnOff, generic Level, ...).
39 Associations of Models with hardware
43 * LED1 is associated with generic OnOff Server's state which is part of Root element
44 * LED2 is associated with Vendor Model which is part of Root element
45 * LED3 is associated with generic Level (ROOT) / Light Lightness Actual value
46 * LED4 is associated with generic Level (Secondary) / Light CTL Temperature value
47 * Button1 and Button2 are associated with gen. OnOff Client or Vendor Model which is part of Root e…
48 * Button3 and Button4 are associated with gen. Level Client / Light Lightness Client / Light CTL Cl…
54 If a server is provided with a publish address, it will
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| /Zephyr-latest/tests/drivers/adc/adc_api/boards/ |
| D | lpcxpresso55s69_lpc55s69_cpu0.overlay | 20 * Channel 0 is used in single ended mode, with 12 bit resolution
34 * Channel 1 is used in single ended mode, with 16 bit resolution
48 * Channel 2 is used in single ended mode, with 12 bit resolution
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| D | lpcxpresso55s69_lpc55s69_cpu0_ns.overlay | 20 * Channel 0 is used in single ended mode, with 12 bit resolution
34 * Channel 1 is used in single ended mode, with 16 bit resolution
48 * Channel 2 is used in single ended mode, with 12 bit resolution
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| /Zephyr-latest/doc/develop/sca/ |
| D | sparse.rst | 10 spaces in C code with subsequent verification that pointers to different
18 Running with sparse
22 called with a ``-DZEPHYR_SCA_VARIANT=sparse`` parameter, e.g.
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| /Zephyr-latest/samples/drivers/counter/alarm/ |
| D | README.rst | 10 It sets an alarm with an initial delay of 2 seconds. At each alarm
11 expiry, a new alarm is configured with a delay multiplied by 2.
20 This sample requires the support of a timer IP compatible with alarm setting.
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| /Zephyr-latest/boards/qemu/x86/ |
| D | qemu_x86_atom_virt_defconfig | 25 # and cannot deal with mapping a stack with virtual
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