Searched refs:well (Results 176 – 200 of 401) sorted by relevance
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| /Zephyr-latest/boards/nxp/rddrone_fmuk66/ |
| D | rddrone_fmuk66.dts | 313 * BMP280 as well.
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| /Zephyr-latest/boards/st/nucleo_f446ze/doc/ |
| D | index.rst | 130 as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz,
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| /Zephyr-latest/boards/adi/eval_adin1110ebz/doc/ |
| D | index.rst | 108 EVAL-ADIN1110EBZ System Clock could be driven by an internal or external oscillator, as well as
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| /Zephyr-latest/doc/develop/api/ |
| D | design_guidelines.rst | 64 occurred, as well as user context which may or may not be the
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| /Zephyr-latest/boards/st/nucleo_h753zi/doc/ |
| D | index.rst | 112 oscillator, as well as the main PLL clock. By default, the System clock is
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| /Zephyr-latest/tests/arch/arm/arm_interrupt/ |
| D | README.txt | 14 - the behavior of the spurious interrupt handler, as well as the
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| /Zephyr-latest/boards/st/nucleo_h7a3zi_q/doc/ |
| D | index.rst | 102 oscillator, as well as the main PLL clock. By default, the System clock is
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| /Zephyr-latest/boards/alientek/pandora_stm32l475/doc/ |
| D | index.rst | 111 as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz,
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| /Zephyr-latest/samples/shields/x_nucleo_iks02a1/microphone/ |
| D | README.rst | 29 Similar consideration may apply to other boards as well.
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| /Zephyr-latest/boards/acrn/acrn/doc/ |
| D | index.rst | 158 additional VMs, you should change their configurations as well.
285 If all goes well, booting your EFI media on the hardware will result
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| /Zephyr-latest/doc/security/ |
| D | security-overview.rst | 285 well established cryptographic libraries shall be used.
370 consistent releases with a well-documented feature set and a
548 vulnerabilities, as well as the description of the potential exploits of
646 evaluated and certified, as well as assumptions on the operating
653 These steps are partially covered in previous sections as well. In
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| /Zephyr-latest/soc/espressif/common/ |
| D | Kconfig.esptool | 35 Mode the flash chip is flashed in, as well as the default mode for the
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| /Zephyr-latest/boards/seeed/lora_e5_mini/doc/ |
| D | index.rst | 88 High-speed internal (HSI) or High-speed external (HSE) oscillator, as well as
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| /Zephyr-latest/boards/others/esp32c3_supermini/doc/ |
| D | index.rst | 8 …ations depending on the specific vendor. For more information a reasonbly well documented version …
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| /Zephyr-latest/arch/posix/ |
| D | CMakeLists.txt | 155 # (supported by current gcc's as well)
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| /Zephyr-latest/doc/services/portability/posix/overview/ |
| D | index.rst | 42 :ref:`SMP <smp_arch>` configuration), as well as
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| /Zephyr-latest/boards/96boards/argonkey/doc/ |
| D | index.rst | 101 96Boards Argonkey can be driven by an internal oscillator as well as the main
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| /Zephyr-latest/boards/actinius/icarus/doc/ |
| D | index.rst | 8 LTE-M, NB-IoT, GPS, accelerometer, USB, LiPo charger as well as
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| /Zephyr-latest/boards/st/stm32f429i_disc1/doc/ |
| D | index.rst | 106 as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 168MHz,
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| /Zephyr-latest/boards/witte/linum/doc/ |
| D | index.rst | 301 oscillator, as well as the main PLL clock. By default, the System clock is
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| /Zephyr-latest/ |
| D | CODE_OF_CONDUCT.md | 96 includes avoiding interactions in community spaces as well as external channels
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| /Zephyr-latest/boards/weact/mini_stm32h7b0/doc/ |
| D | index.rst | 102 as well as by the main PLL clock. By default, the System clock is driven
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| /Zephyr-latest/boards/weact/stm32h5_core/doc/ |
| D | index.rst | 92 as well as by the main PLL clock. By default, the System clock is driven
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| /Zephyr-latest/boards/st/nucleo_f746zg/doc/ |
| D | index.rst | 117 oscillator, as well as the main PLL clock. By default, the System clock is
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| /Zephyr-latest/boards/st/nucleo_f767zi/doc/ |
| D | index.rst | 123 oscillator, as well as the main PLL clock. By default, the System clock is
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