| /Zephyr-latest/include/zephyr/arch/x86/ia32/ |
| D | arch.h | 220 [vector] "i" _VECTOR_ARG(irq_p), \
363 : [vector] "i" (Z_X86_OOPS_VECTOR), \
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| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | CMakeLists.txt | 12 vector.S
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| D | vector_table.ld | 16 * For CONFIG_BOOTLOADER_MCUBOOT, the vector table is located at the
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| /Zephyr-latest/drivers/pcie/host/ |
| D | Kconfig | 51 bool "MSI multi-vector support"
54 support of such capability so each message can get a vector
66 if you want to support multi-vector on MSI-X as well.
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| D | pcie.c | 341 msi_vector_t vector; in pcie_connect_dynamic_irq() local
344 &vector, 1) == 0) || in pcie_connect_dynamic_irq()
345 !pcie_msi_vector_connect(bdf, &vector, in pcie_connect_dynamic_irq()
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| /Zephyr-latest/include/zephyr/arch/sparc/ |
| D | arch.h | 118 : [vector] "i" (SPARC_SW_TRAP_EXCEPT), "r" (_g1) \
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| /Zephyr-latest/tests/arch/arc/arc_vpx_lock/ |
| D | README.txt | 6 code that uses the ARC VPX vector registers works correctly. As this VPX
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| /Zephyr-latest/samples/drivers/virtualization/ivshmem/doorbell/ |
| D | README.rst | 156 int <peer> <vector>: notify one vector on a peer
162 vector 0 is enabled (fd=7)
163 vector 1 is enabled (fd=8)
165 vector 0 is enabled (fd=5)
166 vector 1 is enabled (fd=6)
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| /Zephyr-latest/tests/modules/thrift/ThriftTest/src/ |
| D | client.cpp | 151 vector<int32_t> response_list; in ZTEST()
152 context.client->testList(response_list, vector<int32_t>()); in ZTEST()
155 static const vector<int32_t> request_list = {-2, -1, 0, 1, 2}; in ZTEST()
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| /Zephyr-latest/arch/x86/ |
| D | gen_idt.py | 118 def update_irq_vec_map(irq_vec_map, irq, vector, max_irq): argument
132 debug("assign IRQ %d to vector %d" % (irq, vector))
133 irq_vec_map[irq] = vector
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| /Zephyr-latest/drivers/virtualization/ |
| D | virt_ivshmem.h | 43 uint8_t vector; member
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_loapic.c | 205 unsigned int vector /* vector to copy into the LVT */ in z_loapic_int_vec_set() argument
228 ~LOAPIC_VECTOR) | vector); in z_loapic_int_vec_set()
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| /Zephyr-latest/arch/nios2/ |
| D | Kconfig | 45 bool "Include Reset vector"
48 Include the reset vector stub, which enables instruction/data caches
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| /Zephyr-latest/tests/arch/x86/static_idt/ |
| D | README.txt | 25 ***** Unhandled interrupt vector *****
|
| /Zephyr-latest/doc/hardware/arch/ |
| D | arc-support-status.rst | 92 .. [#f6] currently only ARC VPX scalar port is supported. The support of VPX vector pipeline, VCCM,
98 Zephyr supports a limited form sharing of the VPX vector registers known as
112 The cooperative sharing of the VPX vector registers is selected when
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| /Zephyr-latest/tests/arch/arm/arm_sw_vector_relay/ |
| D | README.txt | 5 This test verifies that the vector table relay feature
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| /Zephyr-latest/arch/xtensa/ |
| D | Kconfig | 18 bool "Build reset vector code"
21 This option controls whether the initial reset vector code is built.
50 bool "Workaround for small vector table entries"
53 constraint of the vector table entry and moved the default
54 handlers to the end of vector table, renaming them to
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| /Zephyr-latest/arch/x86/core/ |
| D | Kconfig.intel64 | 44 int "IDT vector to use for scheduler IPI"
50 int "IDT vector to use for TLB shootdown IPI"
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| /Zephyr-latest/soc/snps/emsk/ |
| D | linker.ld | 16 * DRAM includes the exception vector table at reset, which is at
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| /Zephyr-latest/soc/renesas/ra/ra4m2/ |
| D | sections.ld | 17 /* If DTC is used, put the DTC vector table at the start of SRAM.
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| /Zephyr-latest/soc/renesas/ra/ra4m3/ |
| D | sections.ld | 17 /* If DTC is used, put the DTC vector table at the start of SRAM.
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| /Zephyr-latest/soc/renesas/ra/ra6e1/ |
| D | sections.ld | 17 /* If DTC is used, put the DTC vector table at the start of SRAM.
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| /Zephyr-latest/soc/renesas/ra/ra6m4/ |
| D | sections.ld | 17 /* If DTC is used, put the DTC vector table at the start of SRAM.
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| /Zephyr-latest/soc/renesas/ra/ra6m5/ |
| D | sections.ld | 17 /* If DTC is used, put the DTC vector table at the start of SRAM.
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| /Zephyr-latest/soc/renesas/ra/ra8d1/ |
| D | sections.ld | 17 /* If DTC is used, put the DTC vector table at the start of SRAM.
|
