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Searched refs:sys_write32 (Results 76 – 100 of 191) sorted by relevance

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/Zephyr-latest/soc/litex/litex_vexriscv/
Dsoc.h100 sys_write32(value, addr); in litex_write32()
118 sys_write32(value >> 32, addr); in litex_write64()
119 sys_write32(value, addr + 0x4); in litex_write64()
/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_axi.c76 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_write_data()
83 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_TRI_OFFSET); in gpio_xlnx_axi_write_tri()
250 sys_write32(chan_mask, config->base + IPISR_OFFSET); in gpio_xlnx_axi_pin_interrupt_configure()
259 sys_write32(enabled_interrupts, config->base + IPIER_OFFSET); in gpio_xlnx_axi_pin_interrupt_configure()
305 sys_write32(chan_mask, config->base + IPISR_OFFSET); in gpio_xlnx_axi_get_pending_int()
355 sys_write32(0x0, config->base + IPIER_OFFSET); in gpio_xlnx_axi_init()
358 sys_write32(sys_read32(config->base + IPISR_OFFSET), config->base + IPISR_OFFSET); in gpio_xlnx_axi_init()
361 sys_write32(GIER_GIE, config->base + GIER_OFFSET); in gpio_xlnx_axi_init()
/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_rcar.c64 sys_write32(~val, pfc_base + PFC_RCAR_PMMR); in pfc_rcar_write()
65 sys_write32(val, pfc_base + offs); in pfc_rcar_write()
189 sys_write32(val & ~BIT(bit), pfc_base + bias_reg->puen); in pfc_rcar_set_bias()
192 sys_write32(val | BIT(bit), pfc_base + bias_reg->puen); in pfc_rcar_set_bias()
197 sys_write32(val | BIT(bit), pfc_base + bias_reg->pud); in pfc_rcar_set_bias()
199 sys_write32(val & ~BIT(bit), pfc_base + bias_reg->pud); in pfc_rcar_set_bias()
/Zephyr-latest/drivers/mdio/
Dmdio_dwcxgmac.c63 sys_write32(DMA_MODE_SWR_SET(1u), reg_addr); in dwxgmac_software_reset()
110 sys_write32(reg_data, reg_addr); in mdio_transfer()
115 sys_write32(mdio_addr, reg_addr); in mdio_transfer()
125 sys_write32(mdio_data, reg_addr); in mdio_transfer()
/Zephyr-latest/drivers/dai/intel/alh/
Dalh.c82 sys_write32(sys_read32(ALHASCTL) | ALHASCTL_OSEL(0x3), ALHASCTL); in alh_claim_ownership()
83 sys_write32(sys_read32(ALHCSCTL) | ALHASCTL_OSEL(0x3), ALHCSCTL); in alh_claim_ownership()
97 sys_write32(sys_read32(ALHASCTL) | ALHASCTL_OSEL(0), ALHASCTL); in alh_release_ownership()
98 sys_write32(sys_read32(ALHCSCTL) | ALHASCTL_OSEL(0), ALHCSCTL); in alh_release_ownership()
/Zephyr-latest/drivers/dma/
Ddma_intel_adsp_gpdma.c263 sys_write32(val, reg); in intel_adsp_gpdma_clock_enable()
274 sys_write32(val, reg); in intel_adsp_gpdma_clock_disable()
287 sys_write32(val, reg); in intel_adsp_gpdma_claim_ownership()
289 sys_write32(LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG, DSP_INIT_LPGPDMA(0)); in intel_adsp_gpdma_claim_ownership()
290 sys_write32(LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG, DSP_INIT_LPGPDMA(1)); in intel_adsp_gpdma_claim_ownership()
305 sys_write32(val, reg); in intel_adsp_gpdma_release_ownership()
320 sys_write32(SHIM_CLKCTL_LPGPDMA_SPA, reg); in intel_adsp_gpdma_enable()
336 sys_write32(sys_read32(reg) & ~SHIM_CLKCTL_LPGPDMA_SPA, reg); in intel_adsp_gpdma_disable()
/Zephyr-latest/drivers/ethernet/
Deth_dwmac_stm32h7x.c77 sys_write32(reg_val | BIT(1), reg_addr); in dwmac_bus_init()
82 sys_write32(reg_val | 0x03800000, reg_addr); in dwmac_bus_init()
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_xlnx_zynqmp.c34 sys_write32(sel, base + mio_pin_offset * pins[i].pin); in pinctrl_configure_pins()
Dpinctrl_ti_cc32xx.c33 sys_write32(pincfg & MEM_GPIO_PAD_CONFIG_MSK, DT_INST_REG_ADDR(0) + (pin2pad[pin] << 2U)); in pinctrl_configure_pin()
Dpinctrl_ti_k3.c31 sys_write32(pins[i].value, virt_reg_base + pins[i].offset); in pinctrl_configure_pins()
Dpinctrl_silabs_dbus.c29 sys_write32(pins[i].port | FIELD_PREP(PIN_MASK, pins[i].pin), route_reg); in pinctrl_configure_pins()
/Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/include/adsp/
Dio.h22 sys_write32(val, reg); in io_reg_write()
/Zephyr-latest/soc/nxp/imx/imx8x/adsp/include/adsp/
Dio.h22 sys_write32(val, reg); in io_reg_write()
/Zephyr-latest/soc/nxp/imx/imx8/adsp/include/adsp/
Dio.h22 sys_write32(val, reg); in io_reg_write()
/Zephyr-latest/soc/nxp/imx/imx8m/adsp/include/adsp/
Dio.h22 sys_write32(val, reg); in io_reg_write()
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/
Dio.h22 sys_write32(val, reg); in io_reg_write()
/Zephyr-latest/drivers/pcie/host/
Dmsi.c210 sys_write32(map, (mm_reg_t) &vectors[i].msix_vector->msg_addr); in enable_msix()
211 sys_write32(0, (mm_reg_t) &vectors[i].msix_vector->msg_up_addr); in enable_msix()
212 sys_write32(mdr, (mm_reg_t) &vectors[i].msix_vector->msg_data); in enable_msix()
213 sys_write32(0, (mm_reg_t) &vectors[i].msix_vector->vector_ctrl); in enable_msix()
/Zephyr-latest/drivers/timer/
Dsy1xx_sys_timer.c84 sys_write32(reload_timer_ticks, (base + SY1XX_REG_TIMER_CMP_LO_OFFS)); in sy1xx_sys_timer_reload()
96 sys_write32(conf, base); in sy1xx_sys_timer_cfg_auto_reload()
/Zephyr-latest/soc/sensry/ganymed/sy1xx/common/
Dudma.c55 sys_write32(udma_ctrl_per_cg, SY1XX_UDMA_CTRL_PER_CG); in sy1xx_udma_enable_clock()
97 sys_write32(udma_ctrl_per_cg, SY1XX_UDMA_CTRL_PER_CG); in sy1xx_udma_disable_clock()
Dudma.h76 sys_write32(value, SY1XX_ARCHI_SOC_PERIPHERALS_ADDR + SY1XX_ARCHI_UDMA_OFFSET + in plp_udma_cg_set()
127 #define SY1XX_UDMA_WRITE_REG(udma_base, reg, value) sys_write32(value, udma_base + reg)
/Zephyr-latest/drivers/flash/
Dflash_andes_qspi.c149 sys_write32((sys_read32(QSPI_TFMAT(base)) | in flash_andes_qspi_access()
151 sys_write32(addr, QSPI_ADDR(base)); in flash_andes_qspi_access()
205 sys_write32(tctrl, QSPI_TCTRL(base)); in flash_andes_qspi_access()
207 sys_write32(int_msk, QSPI_INTEN(base)); in flash_andes_qspi_access()
209 sys_write32(opcode, QSPI_CMD(base)); in flash_andes_qspi_access()
751 sys_write32(tx_data, QSPI_DATA(base)); in qspi_andes_irq_handler()
758 sys_write32(INTST_TX_FIFO_INT_MSK, QSPI_INTST(base)); in qspi_andes_irq_handler()
773 sys_write32(INTST_RX_FIFO_INT_MSK, QSPI_INTST(base)); in qspi_andes_irq_handler()
779 sys_write32(INTST_END_INT_MSK, QSPI_INTST(base)); in qspi_andes_irq_handler()
782 sys_write32(0, QSPI_INTEN(base)); in qspi_andes_irq_handler()
/Zephyr-latest/drivers/serial/
Duart_altera_jtag.c173 sys_write32(ctrl_val, config->base + UART_ALTERA_JTAG_CTRL_OFFSET); in uart_altera_jtag_init()
290 sys_write32(ctrl_val, config->base + UART_ALTERA_JTAG_CTRL_OFFSET); in uart_altera_jtag_irq_tx_enable()
309 sys_write32(ctrl_val, config->base + UART_ALTERA_JTAG_CTRL_OFFSET); in uart_altera_jtag_irq_tx_disable()
388 sys_write32(ctrl_val, config->base + UART_ALTERA_JTAG_CTRL_OFFSET); in uart_altera_jtag_irq_rx_enable()
407 sys_write32(ctrl_val, config->base + UART_ALTERA_JTAG_CTRL_OFFSET); in uart_altera_jtag_irq_rx_disable()
Duart_nxp_s32_linflexd.c56 sys_write32(linflexd_ier, POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_poll_out()
78 sys_write32(linflexd_ier, POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_poll_in()
213 sys_write32(linflexd_ier, POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_irq_err_enable()
226 sys_write32(linflexd_ier, POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_irq_err_disable()
/Zephyr-latest/include/zephyr/arch/common/
Dsys_io.h48 static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr) in sys_write32() function
/Zephyr-latest/drivers/interrupt_controller/
Dintc_plic.c267 sys_write32(en_value, en_addr); in plic_irq_enable_set_state()
377 sys_write32(priority, prio_addr); in riscv_plic_set_priority()
389 sys_write32(pend_value, pend_addr); in riscv_plic_irq_set_pending()
554 sys_write32(local_irq, claim_complete_addr); in plic_irq_handler()
570 sys_write32(local_irq, claim_complete_addr); in plic_irq_handler()
573 sys_write32(local_irq, claim_complete_addr); in plic_irq_handler()
597 sys_write32(0U, en_addr + (i * sizeof(uint32_t))); in plic_init()
601 sys_write32(0U, thres_prio_addr); in plic_init()
606 sys_write32(0U, prio_addr + (i * sizeof(uint32_t))); in plic_init()

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