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Searched refs:sys_read32 (Results 76 – 100 of 196) sorted by relevance

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/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/
Dio.h17 return sys_read32(reg); in io_reg_read()
/Zephyr-latest/drivers/serial/
Duart_bcm2711.c72 return sys_read32(base + BCM2711_MU_LSR) & BCM2711_MU_LSR_RX_READY; in bcm2711_mu_lowlevel_can_getc()
77 return sys_read32(base + BCM2711_MU_LSR) & BCM2711_MU_LSR_TX_EMPTY; in bcm2711_mu_lowlevel_can_putc()
157 return sys_read32(uart_data->uart_addr + BCM2711_MU_IO) & 0xFF; in uart_bcm2711_poll_in()
186 rx_data[num_rx++] = sys_read32(uart_data->uart_addr + BCM2711_MU_IO) & 0xFF; in uart_bcm2711_fifo_read()
Duart_nxp_s32_linflexd.c50 linflexd_ier = sys_read32(POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_poll_out()
71 linflexd_ier = sys_read32(POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_poll_in()
208 linflexd_ier = sys_read32(POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_irq_err_enable()
221 linflexd_ier = sys_read32(POINTER_TO_UINT(&config->base->LINIER)); in uart_nxp_s32_irq_err_disable()
/Zephyr-latest/soc/sensry/ganymed/sy1xx/common/
Dudma.c19 uint32_t udma_ctrl_per_cg = sys_read32(SY1XX_UDMA_CTRL_PER_CG); in sy1xx_udma_enable_clock()
61 uint32_t udma_ctrl_per_cg = sys_read32(SY1XX_UDMA_CTRL_PER_CG); in sy1xx_udma_disable_clock()
/Zephyr-latest/include/zephyr/arch/nios2/
Dasm_inline_gcc.h29 static ALWAYS_INLINE uint32_t sys_read32(mm_reg_t addr) in sys_read32() function
/Zephyr-latest/drivers/dma/
Ddma_intel_adsp_gpdma.c258 val = sys_read32(reg) | GPDMA_CTL_DCGD; in intel_adsp_gpdma_clock_enable()
272 uint32_t val = sys_read32(reg) & ~GPDMA_CTL_DCGD; in intel_adsp_gpdma_clock_disable()
285 uint32_t val = sys_read32(reg) | GPDMA_OSEL(0x3); in intel_adsp_gpdma_claim_ownership()
303 uint32_t val = sys_read32(reg) & ~GPDMA_OSEL(0x3); in intel_adsp_gpdma_release_ownership()
322 if (!WAIT_FOR((sys_read32(reg) & SHIM_CLKCTL_LPGPDMA_CPA), 10000, in intel_adsp_gpdma_enable()
336 sys_write32(sys_read32(reg) & ~SHIM_CLKCTL_LPGPDMA_SPA, reg); in intel_adsp_gpdma_disable()
/Zephyr-latest/drivers/gpio/
Dgpio_brcmstb.c62 *value = sys_read32(data->base + GIO_DATA); in gpio_brcmstb_port_get_raw()
101 reg_data = sys_read32(data->base + GIO_DATA); in gpio_brcmstb_port_toggle_bits()
Dgpio_xlnx_axi.c69 return sys_read32(config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_read_data()
243 enabled_interrupts = sys_read32(config->base + IPIER_OFFSET); in gpio_xlnx_axi_pin_interrupt_configure()
249 if (sys_read32(config->base + IPISR_OFFSET) & chan_mask) { in gpio_xlnx_axi_pin_interrupt_configure()
297 interrupt_flags = sys_read32(config->base + IPISR_OFFSET); in gpio_xlnx_axi_get_pending_int()
358 sys_write32(sys_read32(config->base + IPISR_OFFSET), config->base + IPISR_OFFSET); in gpio_xlnx_axi_init()
Dgpio_altera_pio.c59 pin_direction = sys_read32(addr); in gpio_pin_direction()
118 *value = sys_read32((addr)); in gpio_altera_port_get_raw()
271 port_value = sys_read32(addr); in gpio_altera_irq_handler()
Dgpio_stellaris.c59 uint32_t int_stat = sys_read32(GPIO_REG_ADDR(base, GPIO_MIS_OFFSET)); in gpio_stellaris_isr()
144 *value = sys_read32(GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, 0xff)); in gpio_stellaris_port_get_raw()
190 value = sys_read32(GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, 0xff)); in gpio_stellaris_port_toggle_bits()
/Zephyr-latest/include/zephyr/arch/common/
Dsys_io.h43 static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr) in sys_read32() function
/Zephyr-latest/drivers/spi/
Dspi_sifive.c23 uint32_t temp = sys_read32(addr); in sys_set_mask()
106 return !(sys_read32(SPI_REG(dev, REG_TXDATA)) & SF_TXDATA_FULL); in spi_sifive_send_available()
118 uint32_t reg = sys_read32(SPI_REG(dev, REG_RXDATA)); in spi_sifive_recv()
Dspi_opentitan.c133 return !(sys_read32(cfg->base + SPI_HOST_STATUS_REG_OFFSET) & SPI_HOST_STATUS_RXEMPTY_BIT); in spi_opentitan_rx_available()
192 uint32_t rx_word = sys_read32(cfg->base + in spi_opentitan_xfer()
222 while (sys_read32(cfg->base + SPI_HOST_STATUS_REG_OFFSET) in spi_opentitan_init()
/Zephyr-latest/drivers/watchdog/
Dwdt_xilinx_axi.c179 uint32_t twcsr0 = sys_read32(config->base + REG_TWCSR0); in wdt_xilinx_axi_feed()
223 if ((sys_read32(config->base + REG_TWCSR0) & CSR0_WRS) != 0) { in z_impl_hwinfo_get_reset_cause()
242 uint32_t twcsr0 = sys_read32(config->base + REG_TWCSR0); in z_impl_hwinfo_clear_reset_cause()
/Zephyr-latest/drivers/timer/
Dti_dmtimer.c35 #define TI_DM_TIMER_READ(reg) sys_read32(TIMER_BASE_ADDR + TI_DM_TIMER_ ## reg)
49 reg_val = sys_read32(reg); in ti_dm_timer_write_masks()
/Zephyr-latest/include/zephyr/arch/arc/
Dsys-io-common.h59 static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr) in sys_read32() function
/Zephyr-latest/drivers/ethernet/dwc_xgmac/
Deth_dwc_xgmac.c354 reg_val = (sys_read32(reg_addr) & in dwxgmac_dma_mtl_init()
372 reg_val = (sys_read32(reg_addr) & in dwxgmac_dma_mtl_init()
448 reg_val = sys_read32(ioaddr + CORE_MAC_TX_CONFIGURATION_OFST); in eth_dwc_xgmac_update_link_speed()
532 reg_val = (sys_read32(reg_addr) & DMA_MODE_INTM_CLR_MSK); in dwxgmac_irq_init()
886 sys_read32(ioaddr + XGMAC_DMA_BASE_ADDR_OFFSET + DMA_INTERRUPT_STATUS_OFST); in eth_dwc_xgmac_isr()
890 sys_read32(ioaddr + XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(x) + in eth_dwc_xgmac_isr()
917 cntxt_data->dma_interrupt_sts |= sys_read32(reg_addr); in eth_dwc_xgmac_isr()
922 dmach_interrupt_sts = sys_read32(reg_addr); in eth_dwc_xgmac_isr()
939 reg_val = sys_read32(reg_addr); in eth_dwc_xgmac_isr()
947 reg_val = sys_read32(reg_addr); in eth_dwc_xgmac_isr()
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_r8a7795_cpg_mssr.c87 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
100 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
Dclock_control_gd32.c103 cfg = sys_read32(config->base + RCU_CFG0_OFFSET); in clock_control_gd32_get_rate()
141 uint32_t cfg1 = sys_read32(config->base + RCU_CFG1_OFFSET); in clock_control_gd32_get_rate()
/Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/
Dsys_io.h59 static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr) in sys_read32() function
/Zephyr-latest/include/zephyr/arch/arm64/
Dsys_io.h69 static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr) in sys_read32() function
/Zephyr-latest/drivers/interrupt_controller/
Dintc_gicv3_its.c82 uint32_t reg = sys_read32(data->base + GITS_CTLR); in its_force_quiescent()
101 reg = sys_read32(data->base + GITS_CTLR); in its_force_quiescent()
262 ridx = sys_read32(data->base + GITS_CREADR) / sizeof(struct its_cmd_block); in its_queue_full()
304 rd_idx = sys_read32(data->base + GITS_CREADR); in its_post_command()
311 idx = sys_read32(data->base + GITS_CREADR); in its_post_command()
643 reg = sys_read32(data->base + GITS_CTLR); in gicv3_its_init()
/Zephyr-latest/drivers/ethernet/
Dphy_cyclonev.c130 tmpreg = sys_read32(EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); in alt_eth_phy_write_register()
174 tmpreg = sys_read32(EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); in alt_eth_phy_read_register()
183 *rdval = sys_read32(EMAC_GMAC_GMII_DATA_ADDR(p->base_addr)); in alt_eth_phy_read_register()
/Zephyr-latest/include/zephyr/arch/riscv/
Dsys_io.h57 static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr) in sys_read32() function
/Zephyr-latest/soc/microchip/mec/mec172x/
Ddevice_power.c196 ds_ctx.timers[i] = sys_read32(p->addr); in deep_sleep_save_timers()
235 temp = sys_read32(p->addr) & ~(p->stop_mask); in deep_sleep_restore_timers()
270 uint32_t regval = sys_read32(addr); in deep_sleep_save_blocks()

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