Searched refs:sys_read32 (Results 126 – 150 of 196) sorted by relevance
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126 #define SY1XX_UDMA_READ_REG(udma_base, reg) sys_read32(udma_base + reg)
79 #define REG_READ(r) sys_read32((mem_addr_t)(DT_INST_REG_ADDR(0) + (r)))
171 return sys_read32((mm_reg_t)z_nios2_get_register_address(base, regnum)); in _nios2_reg_read()
157 int_status = sys_read32(DMA_INT_STATUS(dev)); in dma_atcdmac300_isr()415 src_width = FIELD_GET(DMA_CH_CTRL_SWIDTH_MASK, sys_read32(DMA_CH_CTRL(dev, channel))); in dma_atcdmac300_reload()433 sys_write32(sys_read32(DMA_CH_CTRL(dev, channel)) | DMA_CH_CTRL_ENABLE, in dma_atcdmac300_transfer_start()
271 data = sys_read32(reg_base + DMAC_PL330_DBGSTATUS); in dma_pl330_start_dma_ch()290 data = sys_read32(reg_base + DMAC_PL330_DBGCMD); in dma_pl330_start_dma_ch()310 } while (((sys_read32(cs0_reg + ch * 8)) & CH_STATUS_MASK) != 0); in dma_pl330_wait()
35 *value = sys_read32(base_address + offset); in reset_rpi_read_register()
47 uint32_t in = sys_read32(drv_data->base_addr); in port_get()
45 return sys_read32(config->input); in neorv32_gpio_read()
316 *data = sys_read32(data_reg); in gpio_latch_inst()318 mode[idx] = sys_read32(mode_reg); in gpio_latch_inst()
53 return sys_read32(config->base + offset); in xlnx_axi_timer_read32()
64 uint32_t temp = sys_read32(addr); in sys_set_mask()
67 return sys_read32(config->reg_addr + offs); in pwm_rcar_read()
53 uint32_t val = sys_read32(reg); in clock_control_wch_rcc_on()
227 temp = sys_read32(reg); in stm32_clock_control_on()520 if ((sys_read32(RCC_REG(pclken->bus)) & pclken->enr) == pclken->enr) { in stm32_clock_control_get_status()
81 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()290 if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr) in stm32_clock_control_get_status()
74 status = sys_read32(config->base + STAT_REG_OFFSET); in xlnx_uartlite_read_status()93 return (sys_read32(config->base + RX_FIFO_OFFSET) & BIT_MASK(8)); in xlnx_uartlite_read_rx_fifo()
72 return sys_read32(config->base + NEORV32_UART_CTRL_OFFSET); in neorv32_uart_read_ctrl()89 reg = sys_read32(config->base + NEORV32_UART_DATA_OFFSET); in neorv32_uart_read_data()
149 sys_write32((sys_read32(QSPI_TFMAT(base)) | in flash_andes_qspi_access()735 intr_status = sys_read32(QSPI_INTST(base)); in qspi_andes_irq_handler()740 spi_status = sys_read32(QSPI_STAT(base)); in qspi_andes_irq_handler()765 rx_data = sys_read32(QSPI_DATA(base)); in qspi_andes_irq_handler()
122 uint32_t pcr_val = sys_read32(addr) & ~BIT(cfg->pcr_pos); in tach_xec_sleep_clr()
79 soc_num_cpus = ((sys_read32(DFIDCCP) >> CAP_INST_SHIFT) & CAP_INST_MASK) + 1; in soc_num_cpus_init()
143 static ALWAYS_INLINE uint32_t sys_read32(mm_reg_t addr) in sys_read32() function
296 (sys_read32(reg_base + REG_PAD_BASE_ADDR))
90 #define REG_READ(r) sys_read32((mem_addr_t)(DT_INST_REG_ADDR(0) + (r)))
109 sys_write32((sys_read32(sam_cfg->dma_base) & 0x0000FFFF) | mrba, sam_cfg->dma_base); in can_sam_init()
28 unsigned int instr = sys_read32(ctx.registers[PC]); in is_bkpt()
