| /Zephyr-latest/drivers/espi/ |
| D | espi_saf_mchp_xec_v2.c | 96 static inline void mchp_saf_cs_descr_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
99 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
102 static inline void mchp_saf_poll2_mask_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
107 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
109 regs->SAF_CS1_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
113 static inline void mchp_saf_cm_prefix_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_cm_prefix_wr() argument
117 regs->SAF_CS0_CM_PRF = val; in mchp_saf_cm_prefix_wr()
119 regs->SAF_CS1_CM_PRF = val; in mchp_saf_cm_prefix_wr()
151 static void saf_protection_regions_init(struct mchp_espi_saf *regs) in saf_protection_regions_init() argument
157 regs->SAF_PROT_RG[0].START = 0U; in saf_protection_regions_init()
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| D | espi_mchp_xec_v2.c | 377 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev); in espi_xec_send_oob() local
385 if (!(regs->OOBTXSTS & MCHP_ESPI_OOB_TX_STS_CHEN)) { in espi_xec_send_oob()
390 if (regs->OOBTXSTS & MCHP_ESPI_OOB_TX_STS_BUSY) { in espi_xec_send_oob()
402 regs->OOBTXL = pckt->len; in espi_xec_send_oob()
403 regs->OOBTXC = MCHP_ESPI_OOB_TX_CTRL_START; in espi_xec_send_oob()
404 LOG_DBG("%s %d", __func__, regs->OOBTXL); in espi_xec_send_oob()
412 if (regs->OOBTXSTS & err_mask) { in espi_xec_send_oob()
413 LOG_ERR("Tx failed %x", regs->OOBTXSTS); in espi_xec_send_oob()
414 regs->OOBTXSTS = err_mask; in espi_xec_send_oob()
424 struct espi_iom_regs *regs = ESPI_XEC_REG_BASE(dev); in espi_xec_receive_oob() local
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| /Zephyr-latest/drivers/spi/ |
| D | spi_xec_qmspi_ldma.c | 72 struct qmspi_regs *regs; member
136 static void qmspi_reset(struct qmspi_regs *regs) in qmspi_reset() argument
144 taps[0] = regs->TM_TAPS; in qmspi_reset()
145 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
146 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
147 malt1 = regs->MODE_ALT1; in qmspi_reset()
148 cstm = regs->CSTM; in qmspi_reset()
149 mode = regs->MODE; in qmspi_reset()
150 regs->MODE = MCHP_QMSPI_M_SRST; in qmspi_reset()
151 while (regs->MODE & MCHP_QMSPI_M_SRST) { in qmspi_reset()
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_sam0_tcc.c | 22 Tcc *regs; member
40 static void wait_synchronization(Tcc *regs) in wait_synchronization() argument
42 while (regs->SYNCBUSY.reg != 0) { in wait_synchronization()
64 Tcc *regs = cfg->regs; in pwm_sam0_set_cycles() local
68 bool inverted = ((regs->DRVCTRL.vec.INVEN & invert_mask) != 0); in pwm_sam0_set_cycles()
83 regs->CCBUF[channel].reg = TCC_CCBUF_CCBUF(pulse_cycles); in pwm_sam0_set_cycles()
84 regs->PERBUF.reg = TCC_PERBUF_PERBUF(period_cycles); in pwm_sam0_set_cycles()
87 regs->CCB[channel].reg = TCC_CCB_CCB(pulse_cycles); in pwm_sam0_set_cycles()
88 regs->PERB.reg = TCC_PERB_PERB(period_cycles); in pwm_sam0_set_cycles()
92 regs->CTRLA.bit.ENABLE = 0; in pwm_sam0_set_cycles()
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| /Zephyr-latest/drivers/usb/device/ |
| D | usb_dc_sam_usbc.c | 104 static volatile Usbc *regs = (Usbc *) DT_INST_REG_ADDR(0); variable
122 if (regs->UESTA[ep_idx] != dev_ep_sta_dbg[0][ep_idx]) { in usb_dc_sam_usbc_isr_sta_dbg()
123 dev_ep_sta_dbg[0][ep_idx] = regs->UESTA[ep_idx]; in usb_dc_sam_usbc_isr_sta_dbg()
128 regs->UDCON, regs->UDINT, regs->UDINTE, in usb_dc_sam_usbc_isr_sta_dbg()
129 regs->UECON[ep_idx], regs->UESTA[ep_idx], in usb_dc_sam_usbc_isr_sta_dbg()
136 regs->UDCON, regs->UDINT, regs->UDINTE, in usb_dc_sam_usbc_isr_sta_dbg()
137 regs->UECON[ep_idx], regs->UESTA[ep_idx]); in usb_dc_sam_usbc_isr_sta_dbg()
177 (regs->UESTA[ep_idx] & USBC_UESTA0_CURRBK(1)) > 0) { in usb_dc_sam_usbc_ep_curr_bank()
186 return (regs->UDCON & USBC_UDCON_DETACH) == 0; in usb_dc_is_attached()
191 int reg = regs->UERST; in usb_dc_ep_is_enabled()
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| /Zephyr-latest/tests/kernel/fpu_sharing/generic/src/ |
| D | float_regs_arm64_gcc.h | 34 static inline void _load_all_float_registers(struct fp_register_set *regs) in _load_all_float_registers() argument
54 : "r" (regs) in _load_all_float_registers()
69 static inline void _store_all_float_registers(struct fp_register_set *regs) in _store_all_float_registers() argument
89 : "r" (regs) in _store_all_float_registers()
108 struct fp_register_set *regs) in _load_then_store_all_float_registers() argument
110 _load_all_float_registers(regs); in _load_then_store_all_float_registers()
111 _store_all_float_registers(regs); in _load_then_store_all_float_registers()
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| D | float_regs_sparc.h | 13 static inline void _load_all_float_registers(struct fp_register_set *regs) in _load_all_float_registers() argument
33 : "r" (®s->fp_volatile) in _load_all_float_registers()
37 static inline void _store_all_float_registers(struct fp_register_set *regs) in _store_all_float_registers() argument
57 : "r" (®s->fp_volatile) in _store_all_float_registers()
63 *regs) in _load_then_store_all_float_registers()
65 _load_all_float_registers(regs); in _load_then_store_all_float_registers()
66 _store_all_float_registers(regs); in _load_then_store_all_float_registers()
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| D | float_regs_arc_gcc.h | 38 static inline void _load_all_float_registers(struct fp_register_set *regs) in _load_all_float_registers() argument
52 : : "r" (regs), "r" (temp), in _load_all_float_registers()
71 static inline void _store_all_float_registers(struct fp_register_set *regs) in _store_all_float_registers() argument
85 : : "r" (regs), "r" (temp), in _store_all_float_registers()
106 *regs) in _load_then_store_all_float_registers()
108 _load_all_float_registers(regs); in _load_then_store_all_float_registers()
109 _store_all_float_registers(regs); in _load_then_store_all_float_registers()
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| D | float_regs_x86_gcc.h | 39 static inline void _load_all_float_registers(struct fp_register_set *regs) in _load_all_float_registers() argument
60 : : "r" (regs) in _load_all_float_registers()
83 _load_then_store_all_float_registers(struct fp_register_set *regs) in _load_then_store_all_float_registers() argument
115 : : "r" (regs) in _load_then_store_all_float_registers()
131 static inline void _store_all_float_registers(struct fp_register_set *regs) in _store_all_float_registers() argument
152 : : "r" (regs) : "memory" in _store_all_float_registers()
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_dw.c | 42 volatile struct dw_ictl_registers * const regs = in dw_ictl_initialize() local
46 regs->irq_inten_l = 0U; in dw_ictl_initialize()
47 regs->irq_inten_h = 0U; in dw_ictl_initialize()
55 volatile struct dw_ictl_registers * const regs = in dw_ictl_isr() local
58 dw_ictl_dispatch_child_isrs(regs->irq_finalstatus_l, in dw_ictl_isr()
62 dw_ictl_dispatch_child_isrs(regs->irq_finalstatus_h, in dw_ictl_isr()
71 volatile struct dw_ictl_registers * const regs = in dw_ictl_intr_enable() local
75 regs->irq_inten_l |= (1 << irq); in dw_ictl_intr_enable()
77 regs->irq_inten_h |= (1 << (irq - 32)); in dw_ictl_intr_enable()
85 volatile struct dw_ictl_registers * const regs = in dw_ictl_intr_disable() local
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| D | intc_irqmp.c | 63 volatile struct irqmp_regs *regs = get_irqmp_regs(); in arch_irq_enable() local
64 volatile uint32_t *pimask = ®s->pimask[0]; in arch_irq_enable()
75 volatile struct irqmp_regs *regs = get_irqmp_regs(); in arch_irq_disable() local
76 volatile uint32_t *pimask = ®s->pimask[0]; in arch_irq_disable()
87 volatile struct irqmp_regs *regs = get_irqmp_regs(); in arch_irq_is_enabled() local
88 volatile uint32_t *pimask = ®s->pimask[0]; in arch_irq_is_enabled()
95 volatile struct irqmp_regs *regs = get_irqmp_regs(); in z_sparc_int_get_source() local
100 source = regs->pextack[0] & IRQMP_PEXTACK_EID; in z_sparc_int_get_source()
113 volatile struct irqmp_regs *regs = get_irqmp_regs(); in irqmp_init() local
115 regs->ilevel = 0; in irqmp_init()
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| /Zephyr-latest/drivers/input/ |
| D | input_xec_kbd.c | 31 struct kscan_regs *regs; member
84 struct kscan_regs *regs = cfg->regs; in xec_kbd_drive_column() local
88 regs->KSO_SEL = MCHP_KSCAN_KSO_ALL; in xec_kbd_drive_column()
91 regs->KSO_SEL = MCHP_KSCAN_KSO_EN; in xec_kbd_drive_column()
94 regs->KSO_SEL = data; in xec_kbd_drive_column()
101 struct kscan_regs *regs = cfg->regs; in xec_kbd_read_row() local
104 return ~(regs->KSI_IN & 0xff); in xec_kbd_read_row()
119 struct kscan_regs *regs = cfg->regs; in xec_kbd_set_detect_mode() local
127 regs->KSI_STS = MCHP_KSCAN_KSO_SEL_REG_MASK; in xec_kbd_set_detect_mode()
143 struct kscan_regs *regs = cfg->regs; in xec_kbd_pm_action() local
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_numicro.c | 31 GPIO_T *regs; member
53 GPIO_T * const regs = cfg->regs; in gpio_numicro_configure() local
103 regs->MODE = (regs->MODE & ~MODE_MASK(pin)) | in gpio_numicro_configure()
105 regs->DBEN = (regs->DBEN & ~BIT(pin)) | (debounce_enable << pin); in gpio_numicro_configure()
106 regs->SMTEN = (regs->SMTEN & ~BIT(pin)) | (schmitt_enable << pin); in gpio_numicro_configure()
107 regs->DINOFF = (regs->DINOFF & ~DINOFF_MASK(pin)) | in gpio_numicro_configure()
109 regs->PUSEL = (regs->PUSEL & ~PUSEL_MASK(pin)) | in gpio_numicro_configure()
119 *value = cfg->regs->PIN & PORT_PIN_MASK; in gpio_numicro_port_get_raw()
130 cfg->regs->DATMSK = ~mask; in gpio_numicro_port_set_masked_raw()
131 cfg->regs->DOUT = value; in gpio_numicro_port_set_masked_raw()
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| D | gpio_davinci.c | 68 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev); in gpio_davinci_configure() local
80 regs->set_data = BIT(pin); in gpio_davinci_configure()
82 regs->clr_data = BIT(pin); in gpio_davinci_configure()
84 regs->dir &= ~(BIT(pin)); in gpio_davinci_configure()
86 regs->dir |= BIT(pin); in gpio_davinci_configure()
95 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev); in gpio_davinci_port_get_raw() local
97 *value = regs->in_data; in gpio_davinci_port_get_raw()
105 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev); in gpio_davinci_port_set_masked_raw() local
107 regs->out_data = (regs->out_data & (~mask)) | (mask & value); in gpio_davinci_port_set_masked_raw()
115 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev); in gpio_davinci_port_set_bits_raw() local
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| /Zephyr-latest/drivers/serial/ |
| D | uart_wch_usart.c | 17 USART_TypeDef *regs; member
31 USART_TypeDef *regs = config->regs; in usart_wch_init() local
59 regs->BRR = divn; in usart_wch_init()
60 regs->CTLR1 = ctlr1; in usart_wch_init()
61 regs->CTLR2 = 0; in usart_wch_init()
62 regs->CTLR3 = 0; in usart_wch_init()
75 USART_TypeDef *regs = config->regs; in usart_wch_poll_in() local
77 if ((regs->STATR & USART_STATR_RXNE) == 0) { in usart_wch_poll_in()
81 *ch = regs->DATAR; in usart_wch_poll_in()
88 USART_TypeDef *regs = config->regs; in usart_wch_poll_out() local
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| D | uart_mchp_xec.c | 183 struct uart_regs *regs; member
292 struct uart_regs *regs = dev_cfg->regs; in set_baud_rate() local
305 lcr_cache = regs->LCR; in set_baud_rate()
306 regs->LCR = LCR_DLAB | lcr_cache; in set_baud_rate()
307 regs->RTXB = (unsigned char)(divisor & 0xff); in set_baud_rate()
309 regs->IER = (unsigned char)((divisor >> 8) & 0x7f); in set_baud_rate()
312 regs->LCR = lcr_cache; in set_baud_rate()
329 struct uart_regs *regs = dev_cfg->regs; in uart_xec_configure() local
343 regs->CFG_SEL &= ~(MCHP_UART_LD_CFG_RESET_VCC | in uart_xec_configure()
346 regs->ACTV |= MCHP_UART_LD_ACTIVATE; in uart_xec_configure()
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| /Zephyr-latest/drivers/led/ |
| D | led_mchp_xec.c | 90 struct xec_bbled_regs * const regs; member
147 struct xec_bbled_regs * const regs = config->regs; in xec_bbled_blink() local
169 regs->config = (regs->config & ~(XEC_BBLED_CFG_MODE_MSK)) in xec_bbled_blink()
171 regs->delay = (regs->delay & ~(XEC_BBLED_DLY_LO_MSK)) in xec_bbled_blink()
173 regs->limits = (regs->limits & ~(XEC_BBLED_LIM_MIN_MSK)) in xec_bbled_blink()
175 regs->config = (regs->config & ~(XEC_BBLED_CFG_MODE_MSK)) in xec_bbled_blink()
177 regs->config |= BIT(XEC_BBLED_CFG_EN_UPDATE_POS); in xec_bbled_blink()
185 struct xec_bbled_regs * const regs = config->regs; in xec_bbled_on() local
191 regs->config = (regs->config & ~(XEC_BBLED_CFG_MODE_MSK)) in xec_bbled_on()
199 struct xec_bbled_regs * const regs = config->regs; in xec_bbled_off() local
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| /Zephyr-latest/drivers/flash/ |
| D | flash_stm32f7x.c | 27 static inline void flush_cache(FLASH_TypeDef *regs) in flush_cache() argument
29 if (regs->ACR & FLASH_ACR_ARTEN) { in flush_cache()
30 regs->ACR &= ~FLASH_ACR_ARTEN; in flush_cache()
35 regs->ACR |= FLASH_ACR_ARTRST; in flush_cache()
36 regs->ACR &= ~FLASH_ACR_ARTRST; in flush_cache()
37 regs->ACR |= FLASH_ACR_ARTEN; in flush_cache()
43 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in write_byte() local
47 if (regs->CR & FLASH_CR_LOCK) { in write_byte()
57 regs->CR = (regs->CR & CR_PSIZE_MASK) | in write_byte()
68 regs->CR &= (~FLASH_CR_PG); in write_byte()
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| D | flash_stm32g0x.c | 43 static inline void flush_cache(FLASH_TypeDef *regs) in flush_cache() argument
45 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
46 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
51 regs->ACR |= FLASH_ACR_ICRST; in flush_cache()
52 regs->ACR &= ~FLASH_ACR_ICRST; in flush_cache()
53 regs->ACR |= FLASH_ACR_ICEN; in flush_cache()
60 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); in write_dword() local
65 if (regs->CR & FLASH_CR_LOCK) { in write_dword()
87 regs->CR |= FLASH_CR_PG; in write_dword()
90 tmp = regs->CR; in write_dword()
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| /Zephyr-latest/soc/microchip/mec/mec172x/ |
| D | timing.c | 24 struct btmr_regs *regs = BTMR_XEC_REG_BASE; in soc_timing_init() local
27 regs->CTRL = MCHP_BTMR_CTRL_ENABLE | MCHP_BTMR_CTRL_AUTO_RESTART | in soc_timing_init()
30 regs->PRLD = 0; /* Preload */ in soc_timing_init()
31 regs->CNT = 0; /* Counter value */ in soc_timing_init()
33 regs->IEN = 0; /* Disable interrupt */ in soc_timing_init()
34 regs->STS = 1; /* Clear interrupt */ in soc_timing_init()
39 regs->CTRL |= MCHP_BTMR_CTRL_START; in soc_timing_start()
44 regs->CTRL &= ~MCHP_BTMR_CTRL_START; in soc_timing_stop()
49 return regs->CNT; in soc_timing_counter_get()
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| /Zephyr-latest/drivers/rtc/ |
| D | rtc_ds1307.c | 48 uint8_t regs[7]; in ds1307_set_time() local
60 regs[0] = bin2bcd(tm->tm_sec) & SECONDS_BITS; in ds1307_set_time()
61 regs[1] = bin2bcd(tm->tm_min); in ds1307_set_time()
62 regs[2] = bin2bcd(tm->tm_hour); in ds1307_set_time()
63 regs[3] = bin2bcd(tm->tm_wday); in ds1307_set_time()
64 regs[4] = bin2bcd(tm->tm_mday); in ds1307_set_time()
65 regs[5] = bin2bcd(tm->tm_mon); in ds1307_set_time()
66 regs[6] = bin2bcd((tm->tm_year % 100)); in ds1307_set_time()
68 err = i2c_burst_write_dt(&config->i2c_bus, DS1307_REG_SECONDS, regs, sizeof(regs)); in ds1307_set_time()
78 uint8_t regs[7]; in ds1307_get_time() local
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| D | rtc_sam.c | 38 Rtc *regs; member
98 Rtc *regs = config->regs; in rtc_sam_set_time() local
111 regs->RTC_IER = RTC_IER_ACKEN; in rtc_sam_set_time()
116 regs->RTC_CR = (RTC_CR_UPDTIM | RTC_CR_UPDCAL); in rtc_sam_set_time()
120 regs->RTC_CR = 0; in rtc_sam_set_time()
125 regs->RTC_IDR = RTC_IDR_ACKDIS; in rtc_sam_set_time()
131 regs->RTC_TIMR = rtc_sam_timr_from_tm(timeptr); in rtc_sam_set_time()
132 regs->RTC_CALR = rtc_sam_calr_from_tm(timeptr); in rtc_sam_set_time()
133 regs->RTC_CR = 0; in rtc_sam_set_time()
135 regs->RTC_IDR = RTC_IDR_ACKDIS; in rtc_sam_set_time()
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_max32.c | 21 mxc_wdt_regs_t *regs; member
57 if (!(cfg->regs->ctrl & WRAP_MXC_F_WDT_CTRL_EN)) { in wdt_max32_disable()
61 MXC_WDT_Disable(cfg->regs); in wdt_max32_disable()
70 MXC_WDT_ResetTimer(cfg->regs); in wdt_max32_feed()
78 if (cfg->regs->ctrl & WRAP_MXC_F_WDT_CTRL_EN) { in wdt_max32_setup()
86 MXC_WDT_ResetTimer(cfg->regs); in wdt_max32_setup()
87 MXC_WDT_Enable(cfg->regs); in wdt_max32_setup()
96 mxc_wdt_regs_t *regs = dev_cfg->regs; in wdt_max32_install_timeout() local
103 if (regs->ctrl & WRAP_MXC_F_WDT_CTRL_EN) { in wdt_max32_install_timeout()
120 ret = Wrap_MXC_WDT_Init(regs, &wdt_cfg); in wdt_max32_install_timeout()
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| /Zephyr-latest/tests/arch/arc/arc_dsp_sharing/src/ |
| D | dsp_regs_arc.h | 34 void _load_all_dsp_registers(struct dsp_register_set *regs) in _load_all_dsp_registers() argument
36 uint32_t *temp = (uint32_t *)regs; in _load_all_dsp_registers()
54 void _store_all_dsp_registers(struct dsp_register_set *regs) in _store_all_dsp_registers() argument
56 uint32_t *temp = (uint32_t *)regs; in _store_all_dsp_registers()
76 void _load_then_store_all_dsp_registers(struct dsp_register_set *regs) in _load_then_store_all_dsp_registers() argument
78 _load_all_dsp_registers(regs); in _load_then_store_all_dsp_registers()
79 _store_all_dsp_registers(regs); in _load_then_store_all_dsp_registers()
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| /Zephyr-latest/drivers/ps2/ |
| D | ps2_mchp_xec.c | 34 struct ps2_regs * const regs; member
112 struct ps2_regs * const regs = config->regs; in ps2_xec_configure() local
127 temp = regs->TRX_BUFF; in ps2_xec_configure()
128 regs->STATUS = MCHP_PS2_STATUS_RW1C_MASK; in ps2_xec_configure()
133 regs->CTRL = MCHP_PS2_CTRL_EN_POS; in ps2_xec_configure()
150 struct ps2_regs * const regs = config->regs; in ps2_xec_write() local
164 while (((regs->STATUS & in ps2_xec_write()
179 regs->CTRL = 0x00; in ps2_xec_write()
182 temp = regs->TRX_BUFF; in ps2_xec_write()
184 regs->STATUS = MCHP_PS2_STATUS_RW1C_MASK; in ps2_xec_write()
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