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Searched refs:regs (Results 101 – 125 of 236) sorted by relevance

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/Zephyr-latest/arch/arc/core/dsp/
DKconfig52 set as default, including 4 address pointers regs, 2 address offset regs
53 and 4 modifiers regs.
59 Save and restore medium AGU registers, including 8 address pointers regs,
60 4 address offset regs and 12 modifiers regs.
67 Save and restore large AGU registers, including 12 address pointers regs,
68 8 address offset regs and 24 modifiers regs.
/Zephyr-latest/drivers/gpio/
Dgpio_ifx_cat1.c31 GPIO_PRT_Type *regs; member
53 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_configure()
103 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_get_raw()
114 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_set_masked_raw()
125 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_set_bits_raw()
136 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_clear_bits_raw()
147 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_toggle_bits()
157 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_get_pending_int()
165 GPIO_PRT_Type *const base = cfg->regs; in gpio_isr_handler()
185 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_pin_interrupt_configure()
[all …]
Dgpio_psoc6.c30 GPIO_PRT_Type *regs; member
45 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_config()
95 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_port_get_raw()
109 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_port_set_masked_raw()
120 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_port_set_bits_raw()
131 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_port_clear_bits_raw()
142 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_port_toggle_bits()
155 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_pin_interrupt_configure()
195 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_isr()
225 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_get_pending_int()
[all …]
Dgpio_sam4l.c26 Gpio *regs; member
45 Gpio * const gpio = cfg->regs; in gpio_sam_port_configure()
106 Gpio * const gpio = cfg->regs; in gpio_sam_port_get_raw()
118 Gpio * const gpio = cfg->regs; in gpio_sam_port_set_masked_raw()
129 Gpio * const gpio = cfg->regs; in gpio_sam_port_set_bits_raw()
140 Gpio * const gpio = cfg->regs; in gpio_sam_port_clear_bits_raw()
151 Gpio * const gpio = cfg->regs; in gpio_sam_port_toggle_bits()
164 Gpio * const gpio = cfg->regs; in gpio_sam_port_interrupt_configure()
201 Gpio * const gpio = cfg->regs; in gpio_sam_isr()
260 .regs = (Gpio *)DT_INST_REG_ADDR(n), \
Dgpio_sam.c27 Pio *regs; member
45 Pio * const pio = cfg->regs; in gpio_sam_port_configure()
165 Pio * const pio = cfg->regs; in gpio_sam_port_get_raw()
177 Pio * const pio = cfg->regs; in gpio_sam_port_set_masked_raw()
187 Pio * const pio = cfg->regs; in gpio_sam_port_set_bits_raw()
199 Pio * const pio = cfg->regs; in gpio_sam_port_clear_bits_raw()
210 Pio * const pio = cfg->regs; in gpio_sam_port_toggle_bits()
224 Pio * const pio = cfg->regs; in gpio_sam_port_interrupt_configure()
278 Pio * const pio = cfg->regs; in gpio_sam_isr()
327 .regs = (Pio *)DT_INST_REG_ADDR(n), \
/Zephyr-latest/drivers/disk/nvme/
Dnvme_controller.c29 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_wait_for_ready() local
36 csts = nvme_mmio_read_4(regs, csts); in nvme_controller_wait_for_ready()
61 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_disable() local
66 cc = nvme_mmio_read_4(regs, cc); in nvme_controller_disable()
67 csts = nvme_mmio_read_4(regs, csts); in nvme_controller_disable()
90 nvme_mmio_write_4(regs, cc, cc); in nvme_controller_disable()
98 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_enable() local
103 cc = nvme_mmio_read_4(regs, cc); in nvme_controller_enable()
104 csts = nvme_mmio_read_4(regs, csts); in nvme_controller_enable()
134 nvme_mmio_write_4(regs, cc, cc); in nvme_controller_enable()
[all …]
/Zephyr-latest/drivers/misc/timeaware_gpio/
Dtimeaware_gpio_intel.c62 static mm_reg_t regs(const struct device *dev) in regs() function
70 *current_time = sys_read32(regs(dev) + ART_L); in tgpio_intel_get_time()
71 *current_time += ((uint64_t)sys_read32(regs(dev) + ART_H) << UINT32_SIZE); in tgpio_intel_get_time()
87 mm_reg_t addr = regs(dev); in tgpio_intel_pin_disable()
105 mm_reg_t addr = regs(dev); in tgpio_intel_periodic_output()
145 mm_reg_t addr = regs(dev); in tgpio_intel_config_external_timestamp()
183 *timestamp = sys_read32(regs(dev) + TCV31_0); in tgpio_intel_read_ts_ec()
184 *timestamp += ((uint64_t)sys_read32(regs(dev) + TCV63_32) << UINT32_SIZE); in tgpio_intel_read_ts_ec()
185 *event_count = sys_read32(regs(dev) + ECCV31_0); in tgpio_intel_read_ts_ec()
186 *event_count += ((uint64_t)sys_read32(regs(dev) + ECCV63_32) << UINT32_SIZE); in tgpio_intel_read_ts_ec()
/Zephyr-latest/drivers/counter/
Dcounter_max32_rtc.c35 mxc_rtc_regs_t *regs; member
72 mxc_rtc_regs_t *regs = cfg->regs; in api_get_value() local
76 sec = regs->sec; in api_get_value()
77 if (regs->sec != sec) { in api_get_value()
78 sec = regs->sec; in api_get_value()
82 subsec = regs->ssec; in api_get_value()
83 if (regs->ssec != subsec) { in api_get_value()
84 subsec = regs->ssec; in api_get_value()
258 .regs = (mxc_rtc_regs_t *)DT_INST_REG_ADDR(_num), \
/Zephyr-latest/drivers/clock_control/
Dclock_control_wch_rcc.c44 RCC_TypeDef *regs; member
50 RCC_TypeDef *regs = config->regs; in clock_control_wch_rcc_on() local
52 uint32_t reg = (uint32_t)(&regs->AHBPCENR + WCH_RCC_CLOCK_ID_OFFSET(id)); in clock_control_wch_rcc_on()
65 RCC_TypeDef *regs = config->regs; in clock_control_wch_rcc_get_rate() local
66 uint32_t cfgr0 = regs->CFGR0; in clock_control_wch_rcc_get_rate()
148 .regs = (RCC_TypeDef *)DT_INST_REG_ADDR(idx), \
/Zephyr-latest/drivers/display/
Ddisplay_gc9x01x.c40 const void *regs; member
232 const struct gc9x01x_regs *regs = config->regs; in gc9x01x_regs_init() local
259 ret = gc9x01x_transmit(dev, GC9X01X_CMD_PWRCTRL2, regs->pwrctrl2, sizeof(regs->pwrctrl2)); in gc9x01x_regs_init()
263 ret = gc9x01x_transmit(dev, GC9X01X_CMD_PWRCTRL3, regs->pwrctrl3, sizeof(regs->pwrctrl3)); in gc9x01x_regs_init()
267 ret = gc9x01x_transmit(dev, GC9X01X_CMD_PWRCTRL4, regs->pwrctrl4, sizeof(regs->pwrctrl4)); in gc9x01x_regs_init()
271 ret = gc9x01x_transmit(dev, GC9X01X_CMD_GAMMA1, regs->gamma1, sizeof(regs->gamma1)); in gc9x01x_regs_init()
275 ret = gc9x01x_transmit(dev, GC9X01X_CMD_GAMMA2, regs->gamma2, sizeof(regs->gamma2)); in gc9x01x_regs_init()
279 ret = gc9x01x_transmit(dev, GC9X01X_CMD_GAMMA3, regs->gamma3, sizeof(regs->gamma3)); in gc9x01x_regs_init()
283 ret = gc9x01x_transmit(dev, GC9X01X_CMD_GAMMA4, regs->gamma4, sizeof(regs->gamma4)); in gc9x01x_regs_init()
287 ret = gc9x01x_transmit(dev, GC9X01X_CMD_FRAMERATE, regs->framerate, in gc9x01x_regs_init()
[all …]
/Zephyr-latest/drivers/spi/
Dspi_max32.c39 mxc_spi_regs_t *regs; member
87 mxc_spi_regs_t *regs = cfg->regs; in spi_configure() local
104 ret = Wrap_MXC_SPI_Init(regs, master_mode, quad_mode, num_slaves, ss_polarity, spi_speed); in spi_configure()
113 ret = MXC_SPI_SetMode(regs, SPI_MODE_3); in spi_configure()
115 ret = MXC_SPI_SetMode(regs, SPI_MODE_2); in spi_configure()
117 ret = MXC_SPI_SetMode(regs, SPI_MODE_1); in spi_configure()
119 ret = MXC_SPI_SetMode(regs, SPI_MODE_0); in spi_configure()
125 ret = MXC_SPI_SetDataSize(regs, SPI_WORD_SIZE_GET(config->operation)); in spi_configure()
133 ret = MXC_SPI_SetWidth(regs, SPI_WIDTH_QUAD); in spi_configure()
136 ret = MXC_SPI_SetWidth(regs, SPI_WIDTH_DUAL); in spi_configure()
[all …]
/Zephyr-latest/tests/kernel/fpu_sharing/generic/src/
Dfloat_context.h71 double regs[16]; /* d0..d15 */ member
75 double regs[16]; /*d16..d31 */ member
119 __int128 regs[16]; /* q0..q15 */ member
123 __int128 regs[16]; /* q16..q31 */ member
/Zephyr-latest/drivers/dma/
Ddma_max32.c21 mxc_dma_regs_t *regs; member
90 ch = max32_dma_ch_index(cfg->regs, channel); in max32_dma_config()
169 channel = max32_dma_ch_index(cfg->regs, channel); in max32_dma_reload()
193 channel = max32_dma_ch_index(cfg->regs, channel); in max32_dma_start()
212 channel = max32_dma_ch_index(cfg->regs, channel); in max32_dma_stop()
230 channel = max32_dma_ch_index(cfg->regs, channel); in max32_dma_get_status()
251 mxc_dma_regs_t *regs = cfg->regs; in max32_dma_isr() local
256 uint8_t channel_base = max32_dma_ch_index(cfg->regs, 0); in max32_dma_isr()
282 if (MXC_DMA_GetIntFlags(regs) == 0) { in max32_dma_isr()
303 ret = Wrap_MXC_DMA_Init(cfg->regs); in max32_dma_init()
[all …]
/Zephyr-latest/tests/kernel/device/src/
Dmmio.c65 mm_reg_t regs; in ZTEST() local
69 regs = DEVICE_MMIO_GET(dev); in ZTEST()
75 zassert_not_equal(regs, 0, "NULL regs"); in ZTEST()
92 zassert_equal(regs, rom->addr, "bad regs"); in ZTEST()
265 mm_reg_t regs = 0; in ZTEST() local
267 device_map(&regs, 0xF0000000, 0x1000, K_MEM_CACHE_NONE); in ZTEST()
269 zassert_not_equal(regs, 0, "bad regs"); in ZTEST()
/Zephyr-latest/drivers/serial/
Duart_renesas_ra8_sci_b.c29 R_SCI_B0_Type * const regs; member
83 if (IS_ENABLED(CONFIG_UART_ASYNC_API) && cfg->regs->CCR0_b.RIE) { in uart_ra_sci_b_poll_in()
87 if (IS_ENABLED(CONFIG_UART_RA_SCI_B_UART_FIFO_ENABLE) ? cfg->regs->FRSR_b.R == 0U in uart_ra_sci_b_poll_in()
88 : cfg->regs->CSR_b.RDRF == 0U) { in uart_ra_sci_b_poll_in()
94 *c = (unsigned char)cfg->regs->RDR; in uart_ra_sci_b_poll_in()
103 while (cfg->regs->CSR_b.TEND == 0U) { in uart_ra_sci_b_poll_out()
106 cfg->regs->TDR_BY = c; in uart_ra_sci_b_poll_out()
113 const uint32_t status = cfg->regs->CSR; in uart_ra_sci_b_err_check()
262 while ((size - num_tx > 0) && cfg->regs->FTSR != 0x10U) { in uart_ra_sci_b_fifo_fill()
266 cfg->regs->TDR_BY = tx_data[num_tx++]; in uart_ra_sci_b_fifo_fill()
[all …]
/Zephyr-latest/soc/intel/intel_adsp/tools/
Dcavstool.py71 self.regs = Regs(self.base)
72 self.regs.CTL = 0x00
73 self.regs.STS = 0x03
74 self.regs.LPIB = 0x04
75 self.regs.CBL = 0x08
76 self.regs.LVI = 0x0c
77 self.regs.FIFOW = 0x0e
78 self.regs.FIFOS = 0x10
79 self.regs.FMT = 0x12
80 self.regs.FIFOL= 0x14
[all …]
/Zephyr-latest/soc/microchip/mec/common/
Dsoc_i2c.c66 struct gpio_regs *regs = MCHP_XEC_GPIO_REG_BASE; in soc_i2c_port_lines_get() local
82 if (regs->CTRL[idx_scl] & BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS)) { in soc_i2c_port_lines_get()
85 if (regs->CTRL[idx_sda] & BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS)) { in soc_i2c_port_lines_get()
/Zephyr-latest/drivers/usb/udc/
Dudc_smartbond.c90 struct smartbond_ep_reg_set *regs; member
275 struct smartbond_ep_reg_set *regs = ep_state->regs; in fill_tx_fifo() local
291 while ((regs->txs & USB_USB_TXS1_REG_USB_TCOUNT_Msk) > 0 && remaining > 0) { in fill_tx_fifo()
292 regs->txd = *src++; in fill_tx_fifo()
312 regs->txc |= (3 << USB_USB_TXC1_REG_USB_TFWL_Pos); in fill_tx_fifo()
315 regs->txc &= ~USB_USB_TXC1_REG_USB_TFWL_Msk; in fill_tx_fifo()
320 regs->txc |= USB_USB_TXC1_REG_USB_LAST_Msk; in fill_tx_fifo()
363 struct smartbond_ep_reg_set *regs = ep_state->regs; in start_rx_packet() local
367 uint8_t rxc = regs->rxc | USB_USB_RXC1_REG_USB_RX_EN_Msk; in start_rx_packet()
375 start_rx_dma(&config->dma_cfg, (uintptr_t)&regs->rxd, in start_rx_packet()
[all …]
/Zephyr-latest/drivers/mdio/
Dmdio_sam.c35 Gmac * const regs; member
53 cfg->regs->GMAC_MAN = (c45 ? 0U : GMAC_MAN_CLTTO) in mdio_transfer()
61 while (!(cfg->regs->GMAC_NSR & GMAC_NSR_IDLE)) { in mdio_transfer()
73 *data_out = cfg->regs->GMAC_MAN & GMAC_MAN_DATA_Msk; in mdio_transfer()
129 cfg->regs->GMAC_NCR |= GMAC_NCR_MPE; in mdio_sam_bus_enable()
136 cfg->regs->GMAC_NCR &= ~GMAC_NCR_MPE; in mdio_sam_bus_disable()
177 .regs = (Gmac *)DT_INST_REG_ADDR(n), \
/Zephyr-latest/drivers/hwinfo/
Dhwinfo_sam_rstc.c58 Rstc *regs = (Rstc *)DT_INST_REG_ADDR(0); in hwinfo_rstc_init() local
68 mode = regs->RSTC_MR; in hwinfo_rstc_init()
80 regs->RSTC_MR = mode; in hwinfo_rstc_init()
/Zephyr-latest/drivers/dac/
Ddac_sam.c36 Dacc *regs; member
57 Dacc *const dac = dev_cfg->regs; in dac_sam_isr()
79 Dacc *const dac = dev_cfg->regs; in dac_sam_channel_setup()
103 Dacc *const dac = dev_cfg->regs; in dac_sam_write_value()
134 Dacc *const dac = dev_cfg->regs; in dac_sam_init()
181 .regs = (Dacc *)DT_INST_REG_ADDR(0),
/Zephyr-latest/drivers/rtc/
Drtc_rv3028.c563 uint8_t regs[3]; in rv3028_alarm_set_time() local
581 regs[0] = bin2bcd(timeptr->tm_min) & RV3028_ALARM_MINUTES_MASK; in rv3028_alarm_set_time()
583 regs[0] = RV3028_ALARM_MINUTES_AE_M; in rv3028_alarm_set_time()
587 regs[1] = bin2bcd(timeptr->tm_hour) & RV3028_ALARM_HOURS_24H_MASK; in rv3028_alarm_set_time()
589 regs[1] = RV3028_ALARM_HOURS_AE_H; in rv3028_alarm_set_time()
593 regs[2] = bin2bcd(timeptr->tm_mday) & RV3028_ALARM_DATE_MASK; in rv3028_alarm_set_time()
595 regs[2] = RV3028_ALARM_DATE_AE_WD; in rv3028_alarm_set_time()
602 return rv3028_write_regs(dev, RV3028_REG_ALARM_MINUTES, &regs, sizeof(regs)); in rv3028_alarm_set_time()
608 uint8_t regs[3]; in rv3028_alarm_get_time() local
617 err = rv3028_read_regs(dev, RV3028_REG_ALARM_MINUTES, &regs, sizeof(regs)); in rv3028_alarm_get_time()
[all …]
/Zephyr-latest/drivers/entropy/
Dentropy_sam.c20 Trng *regs; member
69 Trng *const trng = config->regs; in entropy_sam_get_entropy_internal()
109 Trng * const trng = config->regs; in entropy_sam_get_entropy_isr()
150 Trng *const trng = config->regs; in entropy_sam_init()
176 .regs = (Trng *)DT_INST_REG_ADDR(0),
/Zephyr-latest/soc/atmel/sam/common/
Dsoc_power.c19 Rstc *regs = (Rstc *)DT_REG_ADDR(SAM_DT_RSTC_DRIVER); in sys_arch_reboot() local
23 regs->RSTC_CR = RSTC_CR_KEY_PASSWD in sys_arch_reboot()
/Zephyr-latest/drivers/watchdog/
Dwdt_sam.c35 Wdt *regs; member
51 Wdt * const wdt = config->regs; in wdt_sam_isr()
87 Wdt * const wdt = config->regs; in wdt_sam_disable()
112 Wdt * const wdt = config->regs; in wdt_sam_setup()
220 Wdt * const wdt = config->regs; in wdt_sam_feed()
235 .regs = (Wdt *)DT_INST_REG_ADDR(0),

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